Æthereal project description
Mapping applications to multiprocessor networks on chip
The goal of the project is the research on the system-level design,
targeting on-chip multiprocessors connected by a on-chip
packet-switched network. A special focus is put on the task-level
The project is carried out in a close collaboration with AEthereal
network-on-chip project at Philips Research. The Æthereal project
is concerned with solving the challenges of future on-chip communication.
These challenges have as much to do with semiconductor technology
as with how systems-on-a-chip (SoCs) are currently designed
(the system-level design).
The application mapping project concerns with the task-level scheduling
of dynamic embedded applications on SoCs with both general-purpose (RISC)
and application-specific (ASIP) processors as the basic building blocks.
It also involves high-level modeling of the system with special concern
put on the communication and memory transfers through Æthereal
People involved (from TU/e-EE-ES):
Most of Æthereal publications are available at the home page
of Kees Goossens, the Æthereal project leader: