Master project: Programming Models for NoC-based MPSoC platforms
Description
Network-on-Chip (NOC) based MPSoC platforms are expected to provide an excellent basis for future multi-media applications because of their flexibility and scalability. The hardware architecture of such a multi-processor platform consists of several IP (Intellectual Property) cores interconnected by a scalable on-chip network (NoC). The IP cores can represent different types of processor, memory and I/O nodes.
The seperation of computation and communication by a NoC-based MPSoC poses new challenges (and oppertunities) for programming them. Programming models suitable for dynamic multi-media applications on multi-processor systems are often KPN (Kahn Process Network) or SDF (Synchonous Data Flow) based. These models of computation enable to describe the computation and communication parts in a mathematical way and make parallelism in a multi-media application explicit.
The main objective of this master project is to identify the desirable services that are to be provided by
NoCs, taking into account both the diversity of IP cores as well as the needs for realising the communication between the
tasks expressed as processes in KPN or actors in SDF. A second objective is to investigate the possibilities of reusing
standardised library functions from MPI (Messsage Passinge Interface) and PVM (Parallel Virtual Machine) as the means to
provide these services to a programmer. Next to an extensive literature study on these topics, the master project includes
implementing selected desirable services for the MiniNoC (www.es.ele.tue.nl/~mininoc).
Duration
October 2004 - June 2005
Student:
- Isabel Márquez de la Rosa (Las Palmas University)
Supervisor:
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