Master project: How to reconfigure in NoC-based SoC architectures?
Description
We consider multiprocessor Systems-on-a-Chip (SoC) consisting of a possibly heterogeneous mix of processing and memory components. The communication between processors is implemented by a Network-on-a-Chip (NoC), consisting of network interfaces and routers. NoCs provide a flexible, scalable, and predictable on-chip communication infrastructure. Jobs running on a NoC-based SoC are modeled and implemented as a synchronous dataflow (SDF) graph. SDF graphs allow reasoning about timing behavior of jobs.
Modern multi-media applications are becoming more and more dynamic. This translates to the need for run-time reconfiguration from one mapping of jobs onto a given NoC-based SoC to a new mapping of possibly different or reconfigured jobs onto that SoC. It is important that this reconfiguration of one mapping to another one respects the real-time requirements present in multi-media applications.
The project builds on existing NoC-based SoC simulators and SDF-based programming environments developed at the TU/e and at Philips Research Labs.
Important questions that should be answered are the following:
- How to implement a reconfiguration from one mapping to another respecting real-time requirements of applications?
- How to (formally) model reconfigurations?
- How to analyse these models, aiming at prediction of reconfiguration times?
Duration
December 2003 - August 2004
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