SmartCam project description
Acronym
SmartCam = Smart camera
Name
Smart-Cam: Devices for Embedded Intelligent Cameras
Duration
2002-2006
Goal
The goal of the project is to explor the new architecture for image
processing application by creating an environment for exploring the
design space parametrized by the architectural template and
integrating this with our application mapping environment.
Description
The advent and subsequent popularity of low cost, low power CMOS vision sensors enables
us to integrate processing logic on the camera chip itself, thereby creating so-called
smart sensors. They have an on-chip SIMD data processing array controlled by an off-chip
controller. Smart sensors can execute low-level image processing routines as soon as one
or more image lines are converted; they do not have to wait for the whole image. High level
image processing like feature extraction and object detection and tracking can be performed
with a separate powerful off-chip processor.
Current solutions have several problems. It is totally unclear what the right architectural
parameters are for a given application domain. There are many parameters, like pixel array
size, pixel properties, number of AD-converter units, accuracy, number of pixels per SIMD
processor element, processor element functionality, etc. Also the functionality of the
external processor and its connectivity with the smart sensor has to be determined.Furthermore,
intuitive mappings of algorithms on architecture components are used, after the architecture
has been determined. It will be clear that this is far from optimal. Finally we foresee a
further integration, making a combination of on-chip vision sensor, pixel processing, control,
and feature / object processing possible.The result is a low-cost one-chip smart camera
(so-called SmartCam) solution.This means that research is needed to explore the new
architectural opportunities and consequences.
The SmartCam project investigates these new opportunities and contributes to a better and more
quantitatively guided design trajectory. In particular, we will investigate the impact of
current applications, define relevant architectural parameters and develop an architectural
template, enhance our existing application mapping environments for SIMD and
ILP (Instruction-Level Parallel)processors, and perform two case studies. The work will
focus on creating an environment for exploring the design space parametrized by the architectural
template and integrating this with our application mapping environment.
Partners involved
People involved (from TU/e-EE-ES):
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