Reconfigurable Multi-Processor Network-on-Chip on FPGA
Dealing with real-time constraints is always a
problem in a typical System-on-chip design. It is worsened in a
multi-processor system connected via a network. FPGA
prototyping is a quick way to do a real-time simulation of the
system and identify the potential problems. In this paper we
propose a reconfigurable MPNoC architecture in which both
the network and the processing nodes are configured. The flow
allows for each component to be tested separately prior to
testing the entire design. This allows for quick design
iterations of the system. An example design of such an
architecture that has been mapped onto an FPGA is presented.
- Reconfigurable Multi-Processor Network-on-Chip on FPGA
Akash Kumar, Ido Ovadia, Jos Huisken, Henk Corporaal and Jef van Meerbergen
To appear in: 12th Annual Conference of the Advanced School for Computing and Imaging, Proceedings, pages
xyz-xyz. Lommel, Belgium, 14-16 June 2006. ASCI, Delft, The Netherlands, 2006. (abstract, pdf).
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