Predator: a
predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in
contemporary multi-processor systems-on-chip are increasing. Large
high-speed external memories, such as DDR2 SDRAMs, are shared
between a multitude of IPs to satisfy these requirements at a low
cost per bit. However, SDRAMs have highly variable access times
that depend on previous requests. This makes it difficult to accurately and analytically determine latencies and the useful bandwidth at design time, and hence to guarantee that hard real-time
requirements are met.
The main contribution of this paper is a memory controller design that provides a guaranteed minimum bandwidth and a maximum latency bound to the IPs. This is accomplished using a novel
two-step approach to predictable SDRAM sharing. First, we define
memory access groups, corresponding to precomputed sequences
of SDRAM commands, with known efficiency and latency. Second, a predictable arbiter is used to schedule these groups dynamically at run-time, such that an allocated bandwidth and a maximum
latency bound is guaranteed to the IPs. The approach is general
and covers all generations of SDRAM. We present a modular implementation of our memory controller that is efficiently integrated
into the network interface of a network-on-chip. The area of the
implementation is cheap, and scales linearly with the number of
IPs. An instance with six ports runs at 200 MHz and requires 0.042
mm2 in 0.13µm CMOS technology.
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Predator: a
predictable SDRAM memory controller
Akesson, B., Goossens, K., and Ringhofer, M.
In Proceedings of the 5th
IEEE/ACM international Conference on Hardware/Software Codesign and
System Synthesis (Salzburg, Austria, September 30 - October 03, 2007).
CODES+ISSS '07. ACM, New York, NY, 251-256.
(abstract, pdf).
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