A Monitoring-aware Network-on-Chip Design Flow
Networks-on-chip (NoC) are a scalable interconnect solution for systems on chip and are rapidly becoming reality. Monitoring is a key enabler for debugging or performance analysis and quality-of-service techniques. The NoC design problem and the NoC monitoring problem cannot be treated in isolation. We propose a monitoring-aware NoC design flow able to take into account the monitoring requirements in general. We illustrate our flow with a debug driven monitoring case study of transaction monitoring. By treating the NoC design and monitoring problems in synergy, the area cost of monitoring can be limited to 3-20% in general.
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A Monitoring-aware Network-on-Chip Design Flow
C. Ciordaş, A. Hansson, K.G.W. Goossens, T. Basten.
In V. Muthukumar, editor, Digital System Design, 9th EUROMICRO Conference, DSD 2006, Proceedings, pages 97-104. Dubrovnik, Croatia, 30 August - 1 September 2006. IEEE Computer Society Press, Los Alamitos, CA, USA, 2006. (abstract, pdf).
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