Bringing Communication Networks On Chip: Test and Verification Implications
In this article we present test and verification challenges for system chips that utilise on-chip networks. These systems on a chip (SOCs) and networks on a chip (NOCs) are introduced, where the NOC is exemplified by Philips's ĘTHEREAL NOC architecture. We discuss existing test and verification methods forSOCs and NOCs, and show the particular advantages of using a NOC both for testing and verifying thenetwork, and for testing and verifying the other components of the SOC. This paper is concluded withour experiences with NOCs and a description of on-going work within Philips in this emerging field.
|
