DC-SIMD : Dynamic Communication for SIMD processors
SIMD (single instruction multiple data)-type processors
have been found very efficient in image processing applications, because their repetitive structure is able to exploit the
huge amount of data-level parallelism in pixel-type operations, operating at a relatively low energy consumption rate.
However, current SIMD architectures lack support for dynamic communication between processing elements, which
is needed to efficiently map a set of non-linear algorithms.
An architecture for dynamic communication support has
been proposed, but this architecture needs large amounts of
buffering to function properly. In this paper, three architectures supporting dynamic communication without the need
of large amounts of buffering are presented, requiring 98%
less buffer space. Cycle-true communication architecture
simulators have been developed to accurately predict the
performance of the different architectures. Simulations with
several test algorithms have shown a performance improvement of up to 5x compared to a locally connected SIMD-
processor. Also, detailed area models have been developed,
estimating the three proposed architectures to have an area
overhead of 30-70% compared to a locally connected SIMD
architecture (like the IMAP). When memory is taken into account as well, the overhead is estimated to be 13-28%.
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