NoC Monitoring: Impact on the Design Flow
Networks-on-chip (NoCs) are a scalable interconnect solution to large scale multiprocessor systems on chip and are rapidly becoming reality. As the ratio of embedded cores per I/O pin increases, the run-time observability becomes a bottleneck. Run-time NoC monitoring can alleviate this problem. As NoCs are the result of sophisticated synthesis design flows, monitoring must be taken into account during this process. We present several scalable alternatives for NoC monitoring. The alternatives vary from using physically separated interconnects for user data and monitoring data, to a completely shared single interconnect. For each alternative we evaluate area cost, required design flow modifications, non-intrusiveness and reusability of monitoring resources for application communication traffic. An interesting trade-off is presented showing that what is area efficient requires efforts in modifying the NoC design flow and in achieving non-intrusiveness. All the experiments are done in the context of the Æthereal NoC and design flow.
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NoC Monitoring: Impact on the Design Flow
C. Ciordaş, K.G.W. Goossens, A. Rădulescu, T. Basten.
In 2006 IEEE International Symposium on Circuits and Systems, ISCAS 2006, Proceedings, pages 1981-1984. Kos, Greece, 21-24 May 2006. IEEE Computer Society Press, Los Alamitos, CA, USA, 2006. (abstract, pdf).
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