A Scalable Single-Chip Multi-Processor with On-Chip RTOS Kernel
Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem
of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore
unclear at what level software should be integrated. An example of a single-chip multi-processor for real-time (networked) embedded systems is the multi-microprocessor (MlP). Its architecture consists of a scalable number of
identical master processors and a configurable set of shared co-processors. Additionally, an on-chip real-time operating
system kernel is included to support transparent multi-tasking over the set of master processors. In this paper, we
explore the main design issues of the architecture platform on which the MlP is based. In addition, synthesis results are
presented for a lightweight configuration of this architecture platform.
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