Timing analysis model for network based multiprocessor systems
In this paper an embedded multiprocessor system on top of a network on chip is proposed which is
amenable for timing analysis. This multiprocessor system
is intended for multimedia application that process data
streams. The temporal behavior of applications executed
on this multiprocessor system is derived with a Synchronous
Data Flow (SDF) graph in which computation, communication, buffer sizes as well as arbitration is modeled. This
graph can be transformed in an event graph which is a special case of a Petri net from which properties like the minimal throughput can be derived with results of MaxPlus Linear System Theory [1]. Our main contribution in this paper is an SDF model of the network in which an arbiter is
applied which allows the transfer of a possibly varying but
bounded number of words per period.
- Timing analysis model for network based multiprocessor systems
A.J.M. Moonen, M. Bekooij, J. van Meerbergen
In proceedings of ProRISC, 15th annual Workshop of Circuits, System and Signal Processing, pages 91 - 99, ISBN: 90-73461-43-X, November 25 - 26 2004, Veldhoven, The Netherlands. (abstract,pdf).
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