Run-Time Reconfiguration of Communication in SIMD Architectures
SIMD processors are increasingly used in embedded systems for multi-media applications because of their area- and energy-efficiency. Communication between the processing elements (PEs) in an SIMD processor has remained a cause of inefficiency however; the SIMD concept prescribes that all PEs communicate in the same clock cycle. Existing SIMD architectures solve this problem either by multi-hop communication (causing cycle overhead), or by a fully connected communication network (causing area overhead). To solve the communication bottleneck, we propose a reconfigurable SIMD architecture (RC-SIMD) with a set of delay-lines in the instruction bus, distributing the accesses to the communication network over time. We can (re-)configure the size and number of delay- lines, a specific configuration representing a trade-off between the number of clock cycles and the length of a clock period. Reconfiguration time is typically much less than 1% of the execution time of an algorithm, and the extra configuration hardware is less than 2%. Experiments show that our reconfigurable architecture achieves (on average) more than 10% performance improvement over a non-reconfigurable architecture.
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Run-Time Reconfiguration of Communication in SIMD Architectures
H. Fatemi, B. Mesman, H. Corporaal, T. Basten, P. Jonker.
In 20th International Parallel and Distributed Processing Symposium, IPDPS 2006, 13th Reconfigurable Architectures Workshop, RAW 2006, Proceedings (cd-rom), 4 pages. Rhodes Island, Greece, 25-26 April 2006, IEEE Computer Society Press, Los Alamitos, CA, USA, 2006. (abstract, pdf).
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