Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration
Resources in contemporary systems-on-chip (SoC)
are shared between applications to reduce cost. Access to shared
resources is provided by arbiters that require a small hardware
implementation and must run at high speed. To manage heavily
loaded resources, such as memory channels, it is also important
that the arbiter minimizes over allocation. A Credit-Controlled
Static-Priority (CCSP) arbiter comprised of a rate regulator
and a static-priority scheduler has been proposed for scheduling
access to SoC resources. The proposed rate regulator, however,
is not straight-forward to implement in hardware, and assumes
that service is allocated with infinite precision.
In this paper, we introduce a fast and small hardware
implementation of the CCSP rate regulator and formally prove
its correctness. We also show an efficient way of representing the
allocated service in hardware with finite precision. Based on this
representation, we define and evaluate two allocation strategies,
and derive tight bounds on their respective over allocations.
We show that increasing the precision of the implementation
results in an exponential reduction in maximum over allocation
at the cost of a linear increase in area. We demonstrate that the
allocation strategy has a large impact on the allocation success
rate for use cases with high load. Finally, we compare CCSP
to traditional frame-based approaches and conclude that having
a fine allocation granularity that is decoupled from latency is
essential to manage highly loaded resources in real-time systems.
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