Performance Evaluation of Concurrently Executing Parallel Applications on Multi-Processor Systems
Multi-processors are increasingly being used in modern embedded systems for reasons of power and speed. These
systems have to support a large number of applications and
standards, in different combinations, called use-cases. The key
challenges are designing efficient systems handling all these use-
cases; this requires fast exploration of software and hardware
alternatives with accurate performance evaluation.
In this paper, we present a system-level FPGA-based simulation
methodology for performance evaluation of applications on multi-
processor platforms. We observe that for multiple applications
sharing an MPSoC platform, dynamic arbitration can cause
deadlock in simulation. We use conservative Parallel Discrete
Event Simulation (PDES) for simulation of these use-cases. We
further note that conservative PDES is inefficient so we present a
new PDES methodology that avoids causality errors by detecting
them in advance. We call our new approach as smart conservative
PDES. It is scalable in the number of use-cases and number of
simulated processors and is 15% faster than conservative PDES.
We further present results of a case-study of two real life
applications. We used our simulation technique to do a design
space exploration for optimal buffer space for JPEG and H263
decoders.
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