This project is an initiative of the Electronic Systems group at the Eindhoven University of Technology (TU/e) and part of the PreMaDoNa project.

Overview

This webpage describes a design flow to map throughput constrained applications on a Multi-processor System-on-Chip (MPSoC). It integrates several state-of-the-art mapping and synthesis tools into an automated tool flow (see Figure 1). This flow takes as input a throughput constrained application, modeled with a synchronous dataflow graph, a C-based implementation for each actor in the graph, and a template based architecture description. Using these inputs, the tool flow generates an MPSoC platform tailored to the application requirements and it subsequently maps the application to this platform. The output of the flow is an FPGA programmable bit file. An easily extensible template based architecture is presented, this architecture allows fast and flexible generation of a predictable platform that can be synthesized using the presented tool flow.

This website demonstrates the tool flow with an example and provides the option to download both the MAMPS and SDF³ tools under a GPL license and experiment yourself

Figure 1: the tool flow