An open source SRAM generator was published at the ICCAD conference November 2016. It is the first of its kind, since SRAM module generators are very high-valued IP and are typically developed/owned by major IP companies.

Git repository: github

Paper: acm


In this assignment the goal is to evaluate the usefulness of the OpenRAM platform. This is exercised by creating an SRAM generator for a 28nm FDSOI process. Sub tasks which are envisioned are:

  • Evaluate the usability of the platform, answering questions like: can I also generate a large SRAM within acceptable computer run-times for characterization?
  • Within the provided SRAM architecture, design a number of custom leaf cells, such as a 6T SRAM cell.
  • Investigate whether the given architecture is suitable for 28nm FDSOI.
  • Provide suggestions to improve the generator platform and SRAM architecture, especially for low-voltage operation.
  • Implement the generation of layout, RTL-description (verilog/VHDL), and Liberty file.


  • you have followed 5LIH0 or
  • you have experience in Cadence VLSI design tools such as Virtuoso with spice/spectre
  • you are fluent in python
  • you prefer working in GNU/Linux or another POSIX-compatible OS