For CMOS digital circuit design it is shown that the standard sizing in logic gates is not optimal, when the gates are operated using a supply voltage close to the threshold voltage. A method of sizing for such gates has been investigated in the PhD thesis of Bo Liu.
Above work was carried out for a 40nm CMOS process. This assignment is concerned about repeating that exercise for a 28nm FDSOI process such that a reasonable cell library becomes available for the BrainWave project, where low-voltage operation is key. Before actually executing the work an analysis needs to be done whether the proposed techniques is suitable for an FDSOI process: it may be that the sizing rules need to be revisited.
- you have some experience with digital design tools such as Cadence Virtuoso, spectre/spice, and logic synthesis
- you like to be involved in (semi-) custom VLSI design
- you have an ambition in design automation
- you prefer working in GNU/Linux or another POSIX-compatible OS