To enable evaluation of error sensitivity of a digital design, a method has been devised to inject errors in a design. With this method it is possible to determine the sensitivity for system failure of each flip-flop in a design.
In essence it involves simulation of two instantiations of a design (in this example a Viterbi decoder) within a single testbench, in which all memory elements of each design are compared pairwise on the fly. In one design an error can be injected at any location at any time and by pairwise comparing all memory elements in both designs the propagation of an injected error can be observed over time.
The error injection is performed by inserting an injection circuit in front of all flip-flops:
Evaluating digital systems for error sensitivity this way can be a time consuming simulation task.
Currently we use various simulators and we are finalizing a FPGA based acceleration platform using Altera SoCFPGA Cyclone V. Previously also a Zebu system has been used, but speed was limited due to limited communication speed between host processor and FPGA.
For all platforms the same testbench is used (written in python/MyHDL). The devices under test reside in a simulator or mapped on FPGA. The python testbench contains the error insertion mechanism and the full error propagation analysis besides the functional verification and performance measurement. Therefore co-simulation is applied using VPI (for the simulators) or using a C-level interface (for the Zebu and SoCFPGA).
With the appearance of FPGAs with on-chip high speed CPUs exploiting the very tight coupling of the CPU sub-system and FPGA fabric the bandwidth issue which exists for this error analysis has been reduced substantially, as compared to a Zebu.
As extra benefit multiple DUTs can be inserted in parallel on FPGA, as shown:
With the provided platform one can analyze, fairly exhaustively, the error sensitivity of any hardware design executing a certain algorithm.
For applications in space it is crucial that error resiliency is quantified which is possible with such platform.
So, provided and signal processing algorithm, such as multiple antenna receiving systems with spectral analysis, there exists the need to quantify the error sensitivity. The first part of the assignment is to do that for two or three implementation variants.
The final part of the assignment consists of improving our coarse grain reconfigurable array (CGRA) for error resilience.
Following a literature study on fault analysis and obtaining a overview of error resilience methodologies an specific signal processing function will be selected from the field of wide spectrum radio reception. Such receivers are used in satellites, where error resilience is important since a satellite undergoes quite some radiation.
Using the simulation and emulation platform as described:
Evaluate the error sensitivity for three cases:
Running on ARM (M0 or M4)
Running on CGRA
Running on dedicated HW (optional)
Improve error resilience of the algorithm mapped on the CGRA
Optionally, performance can be improved by transferring certain testbench components to the FPGA jointly with the DUT: in case of the Viterbi decoder this could be the random message bits generation and channel model on one side, and the error propagation map buffering on the other side. This enables running the simulation/execution autonomously for many clock cycles on the FPGA system before communication is required to collect the result. I.e. saving on communication overhead between CPU and FPGA system.
This method of design is actually standard practice when hardware accelerated simulation is perform on systems such as Zebu.
- you prefer working in GNU/Linux familiar with linux device drivers
- you have some experience in RTL level design
- you are proficient in C and python
- you have some experience with either Altera SoCFPGAs or Xilinx Zync ARM-based FPGAs.
starting date is flexible, but preferably a.s.a.p.