Note: this assignment is reserved.

Background

ALS patients are engaged in the most difficult human task at the ends of their lives: dying. Being able to communicate with family and friends, with doctors and carers, may make it possibly a bit less lonely. Peter Desain (Radboud University) develops ways to couple brains and computers that enable communication for patients who are completely paralyzed.

At LowLands a demonstration was given. Have a look at the Dutch NOS report

A new venture MindAffect was created with the goal to bring products based on the developed algorithms.

However, the anticipated devices will likely remain too bulky, and that where you come in.

In our group we have a running project BrainWave for epilepsy and Parkinson’s disease with the goal to create low-power silicon enabling 24/7 monitoring of such patients. For commercialization typically volumes will be too low, therefore we seek for more applications to be integrated with the potential to raise interest.

References:

Assignment

Create a low-power implementation (CPU and maybe hardware acelerators) of the BCI algorithm, as will be provided by Prof. Desain. Evaluate the BCI using an EEG monitoring system, the Mobita of TMSi. Since in the captured EEG signal Gold codes are being used it is possible to obtain a very reliable BCI system.

Approach

Analyze the reference system (coded in Matlab) from Radboud for performance and extract compute kernels which determine performance.

Find candidate kernels of hardware implementation, if needed.

Build a prototype on a small Altera SoCFPGA system and evaluate the prototype for silicon implementation in a 28nm FDSOI process to show feasibility of integration in the BrainWave IC.

Requirements

  • you are willing to travel Radboud University regularly to collaborate
  • you are interested in brain-computer interfaces and have affinity with healthcare
  • you feel challenged by future VLSI technologies in the light of Moore’s law ending.
  • you required basic knowledge in coding theory
  • you are proficient in Matlab, python, C and VHDL or Verilog
  • you prefer working in GNU/Linux or another POSIX-compatible OS

Timing

Starting date is flexible, from July 2017 onwards

Conditions

The formal roles of these partners, as well as a possible compensation for the internship are still to be discussed.

Contact