Final Project

Background

Matrix operations such as QR-decomposition and Singular Value Decomposition are widely used in signal processing and control applications. In recent years several publications can be found in the area of EEG processing and MIMO transceiver systems.

Often a CORDIC (COordinate Rotation DIgital Computer) is used to rotate matrix rows and to obtain zero-valued elements.

Assignment

Analyze the design-space for QRD and SVD processing based on CORDICs. With a constraint on throughput performance, what area and energy figures can be obtained? The work is similar which has been done for QRD in [Vishnoi-QRD-2016] so in this work SVD must be included. In fact a co-processor for QRD and SVD has to be designed in a parameterized form: a hardware description needs to be generated and evaluated for area and energy in 28nm FDSOI technology.

The startng point can be a fully systolic implementation for QRD and SVD which can be time-folded to allow for area optimization.

Approach

To avoid the difficulty of analyzing deeply pipelined cordic structures it is advised to use SDF3 and/or python as an aid in design.

References:

Requirements

  • you feel challenged by hardware design in current VLSI technologies
  • you have completed 5LID0 and/or 5LIH0
  • you have experience in hardware description languages such as Verilog or VHDL.
  • you are proficient in C and python
  • you prefer working in GNU/Linux or another POSIX-compatible OS

Timing

starting date is flexible, from July 2017 onwards

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