Using Python there exist few options for RTL (Register Transfer Level) design of digital systems. One such option is to use MyHDL in which hardware is described and simulated (i.e. executed) in python directly.
As a subsequent step either VHDL or Verilog can be generated for further implementation using VLSI and FPGA design tools. Besides both VHDL and Verilog implementations (for instances after synthesis) can be co-simulated using various simulators, such as Mentor ModelSim, Cadence Incisive, but also open source simulators such as Icarus Verilog and GHDL.
Co-simulation is possible by exploiting a unix pipe based communication between the testbench in Python and the VHDL/Verilog implementation in the simulator.
With the appearance of SoC FPGAs, such as Xilinx Zync and Altera Cyclone V, there are new options for fast co-simulation as opposed to large commercial systems such as Cadence Palladium which are in fact emulation systems.
Due to the tight coupling of an ARM CPU with the FPGA fabric we can synthesize a hardware design for FPGA and have a Python testbench running on the ARM CPU (running Linux). This then forms a low-cost emulation system.
Build a emulation system as described above on a Cyclone V based SoCFPGA which can be used as alternative for co-simulation.
The assignment has two components, which preferably are carried out by two different persons as a single project.
Instead of performing a co-simulation of a testbench with a device-under-test (DUT) in Python and a VHDL/Verilog simulator, the goal is to have the DUT synthesized and implemented in FPGA.
To achieve this a co-emulation interface needs to be designed in hardware, such that the ARM CPU can access all IO signals of the DUT. This forms the first part of the assignment where, if time permits extra features for execution tracing can be added.
The second part involves the design of a Linux kernel driver for the co-emulation hardware such that a Python MyHDL process can control and observe the DUT in hardware.
For both the hardware and software components performance is important. For this it is expected that DMA or burst data transfers between the CPU and FPGA are exploited. For instance in a Cyclone V there is the option to use (two) 128 bit wide AXI interface(s) between CPU and FPGA.
- you have experience in hardware description languages such as Verilog or VHDL.
- you are proficient in C and python
- you prefer working in GNU/Linux or another POSIX-compatible OS
starting date is flexible, from July 2017 onwards
- ir. Jos Huisken - firstname.lastname@example.org