Electroencephalogram (EEG) features are crucial for the seizure detection performance. Distinct EEG activities/patterns occur during the evolution of seizure events. In a study of Lei Wang a wide range of promising EEG features in the time, frequency, time–frequency, and spatio-temporal domains, as well as synchronization-based features were extracted to characterize these patterns.
The performance of seizure detection was evaluated in an epoch-based way on detection quality, but not yet on computational cost in terms of area and power for integration in an embedded system.
The challenge in this assignment is to obtain a cost analysis for the various feature extraction algorithms used. This implies performance analysis of the various functions in C on an embedded processor, such as ARM M4, and mapping a selected set of these functions either in dedicated hardware co-procesors or a coarse grain array such as a CGRA
For the various signal processing functions which are used an initial complexity analysis, using a literature search, needs to be collected. Following this analysis a first ranking of computational cost can be made of all algorithms and a selection of candidates can be made for more detailed cost analysis.
In combination with the qualitative performance of these algorithms an even better cost optimization can be done by inserting the qualitative performance as metric into the cost function.
After selection of some algorithms a deep analysis is neeed with the prime objective to perform the algorithms for as little energy as possible, by mapping these algorithms either on a CGRA or on dedicated hardware.
Between various feature extraction function it may happen that some commonalities exist and that these commonalities can be used jointly by extracting various features. This might complicate cost analysis to some extent but brings a benefit when the results can be reused.
- you feel challenged by hardware design in current VLSI technologies
- you have experience in hardware description languages such as Verilog or VHDL.
- you are proficient in C and python
- you prefer working in GNU/Linux or another POSIX-compatible OS
starting date is a.s.a.p., since we are preparing for a tape-out in autumn 2018.