Publications


Journal article

2012

Andova, S., Georgievska, S. & Trcka, N. (2012). Branching bisimulation congruence for probabilistic systems. Theoretical Computer Science, 413(1), 58-72.
Mousavi, M.R., Basten, A.A., Reniers, M.A. & Chaudron, M.R.V. (2012). Timed-Gamma and its coordination language. Nordic Journal of Computing, ..., submitted / in press.

2011

Voeten, J.P.M., Florescu, O., Huang, J. & Corporaal, H. (2011). Error computation for predictable real-time software synthesis. Simulation, transactions of the Society for Modeling and Simulation International, 87(4), 334-350.
Vermeulen, H.G.H. & Goossens, K.G.W. (2011). Interactive debugging of SOCs with multiple clocks. IEEE Design and Test of Computers, 28(3), 44-51.
Sidorova, N., Stahl, C. & Trcka, N. (2011). Soundness verification for conceptual workflow nets with data: Early detection of errors with the most precision possible. Information Systems, 36(7), 1026-1043.
Vink, J.P. & Haan, G. de (2011). No-reference metric design with machine learning for local compresion artifact level. IEEE Journal of Selected Topics in Signal Processing, 5(2), 297-308.
Goossens, K.G.W. & Marculescu, R. (2011). Special issue on networks-on-chips : design flows and case studies. Design Automation for Embedded Systems, 15(2), 15:87-15:88.
Derin, O., Diken, E. & Fiorin, L. (2011). A middleware approach to achieving fault-tolerance of Kahn process networks on networks-on-chips. International Journal of Reconfigurable Computing1-15.
Gomez Agis, F., Hu, H., Luo, J., Mulvad, H.C.H., Galili, M., Calabretta, N., Oxenløwe, L.K., Dorren, H.J.S. & Jeppesen, P. (2011). Optical switching and detection of 640 Gbits/s optical time-division multiplexed data packets transmitted over 50 km of fiber. Optics Letters, 36(17), 3473-3475.
Hansson, M.A. & Goossens, K.G.W. (2011). A quantitative evaluation of a network on chip design flow for multi-core consumer multimedia applications. Design Automation for Embedded Systems, 15(2), 159-190.
Hansson, M.A., Ekerhult, M., Molnos, A.M., Milutinović, A., Nelson, A.T., Ambrose, J.A. & Goossens, K.G.W. (2011). Design and implementation of an operating system for composable processor sharing. Microprocessors and Microsystems, 35(2), 246-260.
Meijer, M. & Pineda de Gyvez, J. (2011). Body-bias-driven design strategy for area and performance efficient CMOS circuits. IEEE Transactions on VLSI Systems
Pu, Y., He, Y., Ye, Z., Moreno Londono, S., Abbo, A.A., Kleihorst, R.P. & Corporaal, H. (2011). From Xetal-II to Xetal-Pro: On the road towards an ultra low-energy and high throughput SIMD procesor. IEEE Transactions on Circuits and Systems for Video Technology, 21(4), 472-484.
Rodriguez-Vazquez, A., Leenaerts, D.M.W. & Pineda de Gyvez, J. (2011). Introduction to the special issue on the 36th European Solid-State Circuits Conference ESSCIRC. IEEE Journal of Solid-State Circuits, 46(7), 1519-1521.
Stefan, R.A. & Goossens, K.G.W. (2011). A TDM slot allocation flow based on multipath routing in NoCs. Microprocessors and Microsystems, 35(2), 130-138.
Zjajo, A., Tang, Q., Berkelaar, M.R.C.M., Pineda de Gyvez, J., Di Bucchianico, A. & Meijs, N.P. van der (2011). Stochastic analysis of deep-submicrometer CMOS process for reliable circuits designs. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(1), 164-175.

2010

Vandamme, L.K.J., Khalfallaoui, A., Leroy, G. & Velu, G. (2010). Thermal equilibrium noise with 1/f spectrum from frequency independent dielecric losses in barrium strontium titanate. Journal of Applied Physics, 107(5), 053717-1/6.
Aalst, W.M.P. van der, Bratosin, C.C., Sidorova, N. & Trcka, N. (2010). A reference model for grid architectures and its validation. Concurrency and Computation : Practice & Experience, 22(11), 1365-1385.
Voeten, J.P.M., Florescu, O., Huang, J. & Corporaal, H. (2010). Error computation for predictable real-time software synthesis. Simulation1-17.
Basten, A.A. & Ernst, R. (2010). Editorial : Model-driven embedded-system design. ACM Transactions on Embedded Computing Systems, 10(2), 151-154.
Bartels, C.L.L. & Haan, G. de (2010). Smoothness constraints in recursive search motion estimation for picture rate conversion. IEEE Transactions on Circuits and Systems for Video Technology, 20(10), 1310-1319.
Bartels, C.L.L., Cordes, C.N., Riemens, B. & Haan, G. de (2010). A system approach to high quality picture-rate conversion. Journal of the Society for Information Display, 18(11), 922-930.
Kumar, Akash, Mesman, B., Corporaal, H. & Ha, Y. (2010). Iterative probabilistic performance prediction for multi-application multi-processor systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(4), 538-551.
Funk, M., Rozinat, A., Karapanos, E., Alves De Medeiros, A.K. & Koca, A. (2010). In situ evaluation of recommender systems: framework and instrumentation. International Journal of Human-Computer Studies, 68(8), 525-547.
Shabbir, A., Kumar, Akash, Stuijk, S., Mesman, B. & Corporaal, H. (2010). CA-MPSoC : an automated design flow for predictable multi-procesor architectures for multiple applications. Journal of Systems Architecture : the EUROMICRO journal, 56(7), 265-277.
Pourshaghaghi, H.R., Ahmadi, R., Jahed-Motlagh, M.R. & Kia, B. (2010). Experimental realization of a reconfigurable three input, one output logic function based on a chaotic circuit. International Journal of Bifurcation and Chaos in Applied Sciences and Engineering, 20(3), 715-726.
Heinrich, A., Bartels, C.L.L., Vleuten, R.J. van der, Cordes, C.N. & Haan, G. de (2010). Optimization of hierarchical 3DRS motion estimators for picture rate conversion. IEEE Journal of Selected Topics in Signal Processing, 5(2), 262-274.
Berg, A. van den, Ren, P., Marinissen, E.J., Gaydadjiev, G.N. & Goossens, K.G.W. (2010). Bandwidth analysis of functional interconnects used as test access mechanism. Journal of Electronic Testing : Theory and Applications, 26(4), 453-464.
Meijer, M., Pineda de Gyvez, J. & Kapoor, A. (2010). Ultra-low-power digital design with body biasing for low area and performance efficient operation. Journal of Low Power Electronics, 6(4), 521-532.
Moreira, O., Basten, A.A., Geilen, M.C.W. & Stuijk, S. (2010). Buffer sizing for rate-optimal single-rate data-flow scheduling revisited. IEEE Transactions on Computers, 59(2), 188-201.
Pu, Y., Pineda de Gyvez, J., Corporaal, H. & Ha, Y. (2010). An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage. IEEE Journal of Solid-State Circuits, 45(3), 668-680.
Singh, A.K., Srikanthan, Th., Kumar, Akash & Jigang, W. (2010). Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms. Journal of Systems Architecture : the EUROMICRO journal, 56(7), 242-255.

2009

Koca, A., Funk, M., Karapanos, E., Rozinat, A., Aalst, W.M.P. van der, Corporaal, H., Martens, J.B.O.S., Putten, P.H.A. van der, Weijters, A.J.M.M. & Brombacher, A.C. (2009). Soft reliability : an interdisciplinary approach with a user-system focus. Quality and Reliability Engineering International, 25(1), 3-20.
He, Y., Deen, N.G., Sint Annaland, M. van & Kuipers, J.A.M. (2009). Gas-solid turbulent flow in a circulating fluidized bed riser : numerical study of binary particle systems. Industrial and Engineering Chemistry Research, 48(17), 8098-8108.
Fernández-Alcón, J., Ciuhu, C., Kate, W.R.Th. ten, Heinrich, A., Uzunbajakava, N., Krekels, G.A.M., Siem, D. & Haan, G. de (2009). Automatic imaging sysem with decision support for inspection of pigmented skin lesions and melanoma diagnosis. IEEE Journal of Selected Topics in Signal Processing, 3(1), 14-25.
Florescu, O., Voeten, J.P.M., Theelen, B.D. & Corporaal, H. (2009). Patterns for automatic generation of soft real-time system models. Simulation, 85(11/12), 709-733.
Gheorghita, Valentin, Palkovic, M., Hamers, J., Vandecappelle, A., Mamagkakis, S., Basten, A.A., Eeckhout, L., Corporaal, H., Catthoor, F., Vandeputte, F. & De Bosschere, K. (2009). System-scenario-based design of dynamic embedded systems. ACM Transactions on Design Automation of Electronic Systems, 14(1), 3-1-45.
Hansson, M.A., Goossens, K.G.W., Bekooij, M.J.G. & Huisken, J. (2009). CoMPSoC: a template for composable and predictable multi-processor system on chips. ACM Transactions on Design Automation of Electronic Systems, 14(1), 2-1/24.
Hansson, M.A., Wiggers, M., Moonen, A.J.M., Goossens, K.G.W. & Bekooij, M.J.G. (2009). Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis. IET Computers and Digital Techniques, 3(5), 398-412.
Hoes, R.J.H., Basten, A.A., Tham, C.K., Geilen, M.C.W. & Corporaal, H. (2009). Quality-of-service trade-off analysis for wireless sensor networks. Performance Evaluation, 66(3-5), 191-208.
Zjajo, A. & Pineda de Gyvez, J. (2009). Analog automatic test pattern generation for quasi-static structural test. IEEE Transactions on VLSI Systems, 10(17), 1383-1391.

2008

Stuijk, S. & Basten, A.A. (2008). Analyzing concurrency in streaming applications. Journal of Systems Architecture : the EUROMICRO journal, 54(1-2), 124-144.
Stuijk, S., Geilen, M.C.W. & Basten, A.A. (2008). Throughput-buffering trade-off exploration for cyclo-static and synchronous dataflow graphs. IEEE Transactions on Computers, 57(10), 1331-1345.
Stuijk, S., Basten, A.A., Geilen, M.C.W., Ghamarian, A.H. & Theelen, B.D. (2008). Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip. Journal of Systems Architecture : the EUROMICRO journal, 54(3-4), 411-426.
Kumar, Akash, Mesman, B., Theelen, B.D., Corporaal, H. & Yajun, H. (2008). Analyzing composability of applications on MPSoC platforms. Journal of Systems Architecture : the EUROMICRO journal, 54(3-4), 369-383.
Kumar, Akash, Fernando, S.D., Ha, Y., Mesman, B. & Corporaal, H. (2008). Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA. ACM Transactions on Design Automation of Electronic Systems, 13(3), 1-27.
Funk, M. & Hamacher, N. (2008). Concept of automatic usability evaluation of safety-critical interactive systems in the field. i-com : Zeitschrift für interaktive und kooperative Medien, 7(1), 18-23.
Beric, A., Meerbergen, J. van, Haan, G. de & Sethuraman, R. (2008). Memory-cenric video processing. IEEE Transactions on Circuits and Systems for Video Technology, 18(4), 439-452.
Ciordas, C., Hansson, M.A., Goossens, K.G.W. & Basten, A.A. (2008). A monitoring-aware network-on-chip design flow. Journal of Systems Architecture : the EUROMICRO journal, 54(3-4), 397-410.
Gheorghita, Valentin, Basten, A.A. & Corporaal, H. (2008). Application scenarios in streaming-oriented embedded-system design. IEEE Design and Test of Computers, 25(6), 581-589.
Gheorghita, Valentin, Basten, A.A. & Corporaal, H. (2008). Scenario selectrion and prediction for DVS-aware scheduling of multimedia applications. Journal of Signal Processing Systems, 50(2), 137-161.
Shao, L., Zhang, H. & Haan, G. de (2008). An overview and performance evaluation of classification-based least squares trained filters. IEEE Transactions on Image Processing, 17(10), 1772-1782.
Ziari, M., Asselen, O.L.J. van, Jansen, M.A.G., Goossens, J.G.P. & Schoenmakers, P.J. (2008). An FTIR study on the solid-state copolymerization of bis(2-hydroxyethyl)terephthalate and poly(butylene terephthalate) and the resulting copolymers. Macromolecular Symposia, 265(Modern Polymer Spectroscopy), 290-296.

2007

Geilen, M.C.W., Basten, A.A., Theelen, B.D. & Otten, R.H.J.M. (2007). An algebra of Pareto points. Fundamenta Informaticae, 78(1), 35-74.
Denolf, K., Bekooij, M.J.G., Cockx, J., Verkest, D. & Corporaal, H. (2007). Exploiting the expressiveness of cyclo-static dataflow to model multimedia implementations. EURASIP Journal on Advances in Signal Processing, 2007, 84078-1/14.
Denolf, K., Chirila-Rus, A., Schumacher, P., Turney, R., Vissers, K., Verkest, D. & Corporaal, H. (2007). A systematic approach to design low power video codec cores. EURASIP Journal on Embedded Systems, 2007, 64569-1/14.
Goel, S.K., Meijer, M. & Pineda de Gyvez, J. (2007). Efficient testing and diagnosis of faulty power switches in SOCs. IET Computers and Digital Techniques, 1(3), 230-236.
Hansson, M.A., Goossens, K.G.W. & Radulescu, A. (2007). A unified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic. VLSI Design, 2007
Hansson, M.A., Goossens, K.G.W. & Radulescu, A. (2007). Avoiding message-dependent deadlock in network-based systems on chip. VLSI Design, 2007
Huang, J., Voeten, J.P.M. & Corporaal, H. (2007). Predictable real-time software synthesis. Real-Time Systems, 36(3), 159-198.
Terechko, A. & Corporaal, H. (2007). Inter-cluster communication in VLIW architectures. ACM Transactions on Architecture and Code Optimizations, 4(2), 11-1/38.
Ykman-Couvreur, Ch., Nollet, V., Marescaux, T., Brockmeyer, E., Catthoor, F. & Corporaal, H. (2007). Design-time application mapping and platform exploration for MP-SoC customised run-time management. IET Computers and Digital Techniques, 1(2), 120-128.
Zhao, M., Bosma, M. & Haan, G. de (2007). Making the best of legacy video on modern displays. Journal of the Society for Information Display, 15(1), 49-60.

2006

Jess, J.A.G., Kalafala, K., Naidu, S.R., Otten, R.H.J.M. & Visweswariah, C. (2006). Statistical timing for parametric yield prediction of digital integrated circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(11), 2376-2392.
Reymen, I.M.M.J., Hammer, D.K., Kroes, P.A., Aken, J.E. van, Dorst, C.H., Bax, M.F.Th. & Basten, A.A. (2006). A domain-independent descriptive design model and its application to structured reflection on design processes. Research in Engineering Design, 16(4), 147-173.
Fatemi, S.H., Mesman, B., Corporaal, H., Basten, A.A. & Kleihorst, R.P. (2006). RC-SIMD: reconfigurable communication SIMD architecture for image processing applications. Journal of Embedded Computing, 2(2), 167-179.
Palkovic, M., Brockmeyer, E., Vanbroekhoven, P., Corporaal, H. & Catthoor, F. (2006). Systematic preprocessing of data dependent constructs for embedded systems. Journal of Low Power Electronics, 2(1), 9-17.
Pastrnak, M., With, P.H.N. de & Meerbergen, J. van (2006). QoS concept for scalable MPEG-4 video object decoding on multimedia (NoC) chips. IEEE Transactions on Consumer Electronics, 52(4), 1418-1426.
Pavlov, A., Sachdev, M. & Pineda de Gyvez, J. (2006). Week cell detection in deep submicron SRAMs: a programmable detection technique. IEEE Journal of Solid-State Circuits, 41(10), 2334-2343.
Rius, J., Pineda de Gyvez, J. & Meijer, M. (2006). An activity monitor for power/performance tuning of CMOS digital circuits. Journal of Low Power Electronics, 2(1), 80-86.
Zjajo, A., Pineda de Gyvez, J. & Gronthoud, G. (2006). Structural fault modeling and fault detection trhrough Neyman-Pearson decision criteria for analog integrated circuits. Journal of Electronic Testing : Theory and Applications, 22(4-6), 399-409.

2005

Pineda de Gyvez, J., Gronthoud, G. & Amine, R. (2005). Multi-VDD testing for analog circuits. Journal of Electronic Testing : Theory and Applications, 21(3), 311-322.
Aa, T. van der, Jayapala, M., Barat, F., Deconinck, G., Lauwereins, R., Corporaal, H. & Catthoor, F. (2005). Instruction buffering exploration for low energy embedded processors. Journal of Embedded Computing, 1(3), 341-351.
Beric, A., Haan, G. de, Sethuraman, R. & Meerbergen, J. van (2005). An Efficient Picture-Rate Up-Converter. Journal of VLSI Signal Processing, 41(1), 49-63.
Ciordas, C., Basten, A.A., Radulescu, A., Goossens, K.G.W. & Meerbergen, J. van (2005). An Event-based Monitoring Service for Networks on Chip. ACM Transactions on Design Automation of Electronic Systems, 10(4), 702-723.
Gheorghita, Valentin, Corporaal, H. & Basten, A.A. (2005). Iterative compilation for energy reduction. Journal of Embedded Computing, 1(4), 509-520.
Jayapala, M., Barat, F., Aa, T. van der, Catthoor, F., Corporaal, H. & Deconinck, G. (2005). Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors. IEEE Transactions on Computers, 54(6), 672-683.
Peters, H., Sethuraman, R., Beric, A., Meeuwissen, P., Balakrishnan, S., Alba Pinto, C.A., Kruijtzer, W., Ernst, F., Alkadi, G., Meerbergen, J. van & Haan, G. de (2005). Application specific instruction-set processor template for motion estimation in video applications. IEEE Transactions on Circuits and Systems for Video Technology, 15(4), 508-527.

2004

Basten, A.A., Bosnacki, D. & Geilen, M.C.W. (2004). Cluster-based partial-order reduction. Automated Software Engineering, 11(4), 365-402.
Jiang, X., Schoenmakers, P.J., Lou, X., Lima, V.G.R., Dongen, J.L.J. van & Brokken, J. (2004). Separation and characterization of functional poly(n-butyl acrylate) by critical liquid chromatography. Journal of Chromatography, A, 1055(1-2), 123-133.
Puttenstein, J.G., Heynderickx, I.E.J. & Haan, G. de (2004). Evaluation of objective quality measures for noise reduction in TV-systems. Signal Processing, 19(2), 109-119.
Villareal, S.S., Pineda de Gyvez, J. & Weichold, M.H. (2004). A CMOS implementation of a 1-bit multi-cell encoded-cellular neural network. Analog Integrated Circuits and Signal Processing, 39(1), 95-108.

2003

Jess, J.A.G. (2003). Performance controlled compilation for embedded signal processors. IT - Information Technology, 45(6), 327-335.
Jiang, X., Lima, V.G.R. & Schoenmakers, P.J. (2003). Robust isocratic liquid chromatographic separation of functional poly(methyl methacrylate). Journal of Chromatography, A, 1018(1), 19-27.
Jiang, X., Schoenmakers, P.J., Dongen, J.L.J. van, Lou, X., Lima, V.G.R. & Brokken, J. (2003). Mass spectrometric characterization of functional poly(methyl methacrylate) in combination with critical liquid chromatography. Analytical Chemistry, 75(20), 5517-5524.
Klompenhouwer, M.A. & Haan, G. de (2003). Subpixel image scaling for color-matrix displays. Journal of the Society for Information Display, 11(1), 99-108.
Naidu, S.R. & Chandru, V. (2003). On Synthesis of (k,K) Circuits. IEEE Transactions on Computers, 52(11), 1490-1494.
Naidu, S.R. (2003). Algebraic Factoring algorithm to recognise read-once functions. IEE Proceedings - Computers and Digital Techniques3, 150-156.
Rijpkema, E., Goossens, K.G.W., Radulescu, A., Dielissen, J.T.M.H., Meerbergen, J. van, Wielage, P. & Waterlander, E. (2003). Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip. IEE Proceedings. Part E, Computers and Digital Techniques, 150(5), 294-302.
Zhao, Q., Mesman, B. & Basten, A.A. (2003). Static resource models for code-size efficient embedded processors. ACM Transactions on Embedded Computing Systems, 2(2), 219-250.

2002

Otten, R.H.J.M. (2002). Shifts in INTEGRATION: 20 years of VLSI design. Integration : the VLSI Journal, 32(1-2), 1-4.
Aalst, W.M.P. van der & Basten, A.A. (2002). Inheritance of workflows : an approach to tackling problems related to change. Theoretical Computer Science, 270(1-2), 125-203.
Haan, G. de (2002). Signalverarbeitungstechniken zur Verbesserung der Bilddarstellung. Fernseh- und Kinotechnik, 1(2), 31-40.
Haan, G. de (2002). Signalverarbeitungstechniken zur Verbesserung der Biddarstellung. Fernseh- und Kinotechnik, 1-2, 31-40.
Bruin, F.J. de, Bruls, W.H.A., Burazerovic, D. & Haan, G. de (2002). Efficient video coding integrating MPEG-2 and picture-rate conversion. IEEE Transactions on Consumer Electronics, 48(3), 688-693.
Kisuki, T., Corporaal, H. & Knijnenburg, P.M.W. (2002). Branch history register cache. Journal of Scheduling, 5(5), 413-424.
Rutten, M.J., Eijndhoven, J.T.J. van, Pol, E-J.D., Jaspers, E.G.T., Wolf, P. v d, Gangwal, O.P. & Timmer, A. (2002). Eclipse: A Heterogeneous Multiprocessor Architecture for Flexible Media Processing. IEEE Design and Test of Computers, 19(4), 39-50.

2001

Verbeek, H.M.W., Basten, A.A. & Aalst, W.M.P. van der (2001). Diagnosing workflow processes using Woflan. The Computer Journal, 44(4), 246-279.
Geilen, M.C.W., Voeten, J.P.M., Putten, P.H.A. van der, Bokhoven, L.J. van & Stevens, M.P.J. (2001). Object-oriented modelling and specification using SHE. Computer Languages, 27(1-3), 19-38.
Basten, A.A. & Aalst, W.M.P. van der (2001). Inheritance of behavior. Journal of Logic and Algebraic Programming, 47(2), 47-145.
Haan, G. de & Klompenhouwer, M.A. (2001). An overview of flaws in emerging television displays and remedial video processing. IEEE Transactions on Consumer Electronics, 47(3), 326-334.
Bellers, E.B. & Haan, G. de (2001). On scanning format and MPEG-2 coding efficiency. Smpte Journal, 110(5), 65-71.
Bellers, E.B. & Haan, G. de (2001). On video formats and coding efficiency. IEEE Transactions on Consumer Electronics, 47(1), 25-32.
Bellers, E.B. & Haan, G. de (2001). On video format and MPEG-2 coding efficiency. Smpte Journal, 110(5), 293-298.
Bellers, E.B., Weert, I. de, Haan, G. de & Heynderickx, I.E.J. (2001). Optimal television scanning format for CRT-displays. IEEE Transactions on Consumer Electronics, 47(3), 347-353.
Wittebrood, R.B & Haan, G. de (2001). Real-time recursive motion segmentation of video data on a programmable device. IEEE Transactions on Consumer Electronics, 47(3), 559-567.

2000

Otten, R.H.J.M. & Brayton, R.K. (2000). Performance planning. Integration : the VLSI Journal, 29(1), 1-24.
Jess, J.A.G. (2000). Designing electronic engines with electronic engines : 40 years of bootstrapping of a technology upon itself. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(12), 1404-1427.
Haan, G. de (2000). Progress in motion estimation for video format conversion. IEEE Transactions on Consumer Electronics, 46(3), 449-459.
Haan, G. de (2000). Large-display video format conversion. Journal of the Society for Information Display, 8(1), 79-90.
Haan, G. de (2000). Large-display video format conversion. Journal of the Society for Information Display, 8(1), 79-87.
Corporaal, H., Janssen, J.A.A.J. & Arnold, M. (2000). Computation in the context of transport triggered architectures. International Journal of Parallel Processing, 28(4), 401-427.
Cilio, A.G.M. & Corporaal, H. (2000). Link-time effective whole-program optimizations. Future Generation Computer Systems, 16(5), 503-511.
Eijk, C.A.J. van (2000). Sequential equivalence checking based on structural similarities. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(7), 814-819.
Eijk, C.A.J. van, Mesman, B., Alba Pinto, C.A., Zhao, Q., Bekooij, M.J.G., Meerbergen, J. van & Jess, J.A.G. (2000). Constraint analysis for code generation : Basic techniques and applications in FACTS. ACM Transactions on Design Automation of Electronic Systems, 5(4), 774-793.
Jongeneel, D.-J. & Otten, R.H.J.M. (2000). Technology mapping for area and speed. Integration : the VLSI Journal, 29(1), 45-66.
Manganaro, G. & Pineda de Gyvez, J. (2000). Nonlinear computability based on chaos. International Journal of Bifurcation and Chaos in Applied Sciences and Engineering, 10(2), 415-429.
Santos, L.C.V. dos, Heijligers, M.J.M., Eijk, C.A.J. van, Eijndhoven, J.T.J. van & Jess, J.A.G. (2000). A code motion pruning technique for global scheduling. ACM Transactions on Design Automation of Electronic Systems, 5(1), 1-38.
Strik, M.T.J., Timmer, A.H., Meerbergen, J. van & Roostelaar, G.J. van (2000). Heterogeneous multiprocessor for the management of real-time video and graphics streams. IEEE Journal of Solid-State Circuits, 35(11), 1722-1731.
Wittebrood, R.B & Haan, G. de (2000). Second generation video format conversion software for a Digital Signal Processor. IEEE Transactions on Consumer Electronics, 46(3), 857-865.

1999

With, P.H.N. de, Jaspers, E.G.T., Meerbergen, J. van, Timmer, A.H. & Strik, M.T.J. (1999). A video display processing platform for future TV concepts. IEEE Transactions on Consumer Electronics, 45(4), 1230-1240.
Mesman, B., Timmer, A.H., Meerbergen, J. van & Jess, J.A.G. (1999). Constraint analysis for DSP code generation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(1), 44-57.
Corporaal, H. (1999). Missing the ILP complexity wall. Journal of Systems Architecture : the EUROMICRO journal, 45(12/13), 949-973.
Corporaal, H. (1999). TTAs: Missing the ILP complexity wall. Journal of Systems Architecture : the EUROMICRO journal, 45(12/13), 949-973.
Moreira-Tamayo, O. & Pineda de Gyvez, J. (1999). Subband coding and image compression using CNN. International Journal of Circuit Theory and Applications, 27(1), 135-151.

1998

Haan, G. de & Biezen, P.W.A.C. (1998). An efficient true-motion estimator using candidate vectors from a parametric motion model. IEEE Transactions on Circuits and Systems for Video Technology, 8(1), 85-91.
Corporaal, H. & Arnold, M. (1998). Using transport triggered architectures for embedded processor design. Integrated Computer-Aided Engineering, 5(1), 19-38.
Arts, H.M.A.M., Berkelaar, M.R.C.M. & Eijk, C.A.J. van (1998). Computing observability don't cares efficiently through polarization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(7), 573-581.
Karkowski, I. & Corporaal, H. (1998). Overcoming the limitations of the traditional loop parallelization. Future Generation Computer Systems, 13(4-5), 407-416.
Nijssen, R.X.T. & Eijk, C.A.J. van (1998). GreyHound : a methodology for utilizing datapath regularity in standard cell design flows. Integration : the VLSI Journal, 25(2), 111-135.
Verhaegh, W.F.J., Lippens, P.E.R., Aarts, E.H.L., Meerbergen, J. van & Werf, A. van der (1998). The complexity of multidimensional periodic scheduling. Discrete Applied Mathematics, 89(1-3), 213-242.
Villareal, S.S., Weichold, M.H. & Pineda de Gyvez, J. (1998). Simulation study of compact quantising circuits using multiple-resonant tunnelling transistors. Electronics Letters, 34(2), 161-162.
Wang, Lei, Pineda de Gyvez, J. & Sanchez-Sinencio, E. (1998). Time multiplexed color image processing based on a CNN with cell-state outputs. IEEE Transactions on VLSI Systems, 6(2), 314-322.

1997

Eijk, C.A.J. van (1997). A BDD-based verification method for large synthesized circuits. Integration : the VLSI Journal, 23(2), 131-149.

1996

Berkelaar, M.R.C.M., Buurman, H.W. & Jess, J.A.G. (1996). Computing the entire area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(11), 1424-1434.
Chan, E., Pineda de Gyvez, J. & Moreira-Tamayo, O. (1996). A time-varying bandpass filter for spectrum analysis. Meta-Software Journal, 2(3), 5-9.
Di, C. & Jess, J.A.G. (1996). An efficient CMOS bridging fault simulator with SPICE accuracy. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(9), 1071-1080.
Fong, A.Q., Kanji, A. & Pineda de Gyvez, J. (1996). Time-multiplexing scheme for cellular neural networks based image processing. Real-Time Imaging, 2(4), 231-239.

1995

Pineda de Gyvez, J. & Cheek, G. (1995). Advanced Yield Modeling. IEEE Transactions on Semiconductor Manufacturing, 8(2), 93-94.
Huijbregts, E.P., Xue, H. & Jess, J.A.G. (1995). Routing for reliable manufacturing. IEEE Transactions on Semiconductor Manufacturing, 8, 188-194.
Verhaegh, W.F.J., Lippens, P.E.R., Aarts, E.H.L., Korst, J.H.M., Meerbergen, J. van & Werf, A. van der (1995). Improved force-directed scheduling in high-throughput digital signal processing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14(8), 945-960.

1992

Pineda de Gyvez, J. & Di, C. (1992). IC defect sensitivity for footprint-type spot defects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(5), 638-658.
Janssen, J.G.M., Snijders, H.M.J., Cramers, C.A.M.G. & Schoenmakers, P.J. (1992). Compressibility effects in packed and open tubular gas and supercritical fluid chromatography. Journal of High Resolution Chromatography, 15(7), 458-466.

1991

Janssen, J.G.M., Schoenmakers, P.J. & Cramers, C.A.M.G. (1991). Mobile and stationary phases for SFC: effects of using modifiers. Mikrochimica Acta, 2(1-6), 337-351.
Janssen, J.G.M., Schoenmakers, P.J. & Cramers, C.A.M.G. (1991). Effects of modifiers in packed and open-tubular supercritical fluid chromatography. Journal of Chromatography, A, 552(1-2), 527-537.
Janssen, J.G.M., Snijders, H.M.J., Rijks, J.A., Cramers, C.A.M.G. & Schoenmakers, P.J. (1991). The effects of the column pressure drop on retention and efficiency in packed and open tubular supercritical fluid chromatography. Journal of High Resolution Chromatography, 14(7), 438-445.

1989

Pineda de Gyvez, J. & Jess, J.A.G. (1989). On the design and implementation of a wafer yield editor. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(8), 920-925.
Janssen, J.G.M., Schoenmakers, P.J. & Cramers, C.A.M.G. (1989). A fundamental study of the effects of modifiers in supercritical fluid chromatography. Journal of High Resolution Chromatography, 12(10), 645-651.

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Book - Monograph

2011

Kumar, Akash, Corporaal, H., Mesman, B. & Ha, Y. (2011). Multimedia multiprocessor systems : analysis, design and management. New York: Springer, 163 p. pp.
Akesson, K.B. & Goossens, K.G.W. (2011). Memory controllers for real-time embedded systems : predictable and composable real-time systems. Berlin: Springer, 221 pp.
Hansson, M.A. & Goossens, K.G.W. (2011). On-chip interconnect with ealite : composable and predictable systems. Berlin: Springer.
Zjajo, A. & Pineda de Gyvez, J. (2011). Low-power high-resolution analog to digital converters : design, test and calibration. Berlin: Springer.

2010

Baeten, J.C.M., Basten, A.A. & Reniers, M.A. (2010). Process algebra : equational theories of communicating processes. Cambridge: Cambridge University Press.
Hansson, M.A. & Goossens, K.G.W. (2010). On-Chip Interconnect with Aelite : Composable and Predictable Systems. Berlin: Springer.
Hansson, M.A. & Goossens, K.G.W. (2010). On-chip interconnect with aelite : composable and predictable systems. Heidelberg: Springer, 220 pp.

2007

Ditzel, M., Otten, R.H.J.M. & Serdijn, W.A. (2007). Power-aware architecting for data-dominated applications. Berlin: Springer Verlag, 118 pp.
Sachdev, M. & Pineda de Gyvez, J. (2007). Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits.Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits. (2nd Edition). Berlin: Springer.

2006

Sachdev, M. & Pineda de Gyvez, J. (2006). Defect-Oriented testing for Nanometric CMOS Circuits. Berlin: Springer.

2000

Haan, G. de (2000). Video processing for multimedia systems. Eindhoven: University Press Eindhoven, 246 pp.
Haan, G. de (2000). Digital video post processing. Eindhoven: G. de Haan, 294 pp.
Bellers, E.B. & Haan, G. de (2000). De-interlacing: A key technology for scan conversion. Amsterdam: Elsevier.

1998

Hurk, J.A.A.M. van den & Jess, J.A.G. (1998). System level hardware/software co-design: an industrial approach. Dordrecht, Netherlands: Kluwer Academic Publishers, 223 pp.

1993

Pineda de Gyvez, J. (1993). Integrated Circuit Defect-Sensitivity: Theory and Computational Models. Berlin: Springer.

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Edited book

2011

Stuijk, S. (Ed.).(2011). SCOPES '11 International Workshop on Software and Compilers for Embedded Systems St. Goar, Germany — June 27 - 28, 2011. New York: ACM, 75 pp.

2007

Basten, A.A., Juhas, G. & Shukla, S. (Eds.).(2007). Application of Concurrency to System Design. Los Alamitos: IEEE Computer Society Press.

2006

Reis, R., Lubaszewski, M. & Jess, J.A.G. (Eds.).(2006). Design of systems on a chip : design and test. Berlin: Springer.

2004

Jess, J.A.G. (Ed.).(2004). Designs of System on a Chip. New York: Kluwer, 270 pp.

2003

Basten, A.A., Geilen, M.C.W. & Groot, H. de (Eds.).(2003). Ambient Intelligence: Impact on Embedded System Design. Boston, USA: Kluwer Academic Publishers, 348 pp.

1998

Pineda de Gyvez, J. & Pradhan, D. (Eds.).(1998). Integrated circuit manufacturability : the art of process and design integration. Chichester: Wiley-IEEE Press, 332 p. pp.

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Book chapter

2011

Jordans, R., Siyoum, F.M., Stuijk, S., Kumar, Akash & Corporaal, H. (2011). An automated flow to map throughput constrained applications to a MPSoC. In P. Lucas, L. Thiele, B. Triquet, T. Ungerer & R. Wilhelm (Eds.), Bringing theory to practice : predictability and performance in embedded systems. (pp. 47-58) Dagstuhl Publishing: Leibniz-Zentrum fuer Informatik.
Trcka, N., Pechenizkiy, M. & Aalst, W.M.P. van der (2011). Process mining from educational data (Chapter 9). In C. Romero, S. Ventura, M. Pechenizkiy & R. Baker (Eds.), Handbook of Educational Data Mining. (pp. 123-142) London: CRC Press.
Corvino, R., Gamatié, A. & Boulet, P. (2011). Design space exploration for efficient data intensive computing on SoCs. In B. Furht & A. Escalante (Eds.), Handbook of data intensive computing. (pp. 581-616) New York: Springer.

2010

Geilen, M.C.W. & Basten, A.A. (2010). Kahn Process Networks and a Reactive Extension. In S.S. Bhattacharyya, E.F. Deprettere, R. Leupers & J. Takala (Eds.), Handbook of Signal Processing Systems. (pp. 967-1006) Berlin: Springer.
Vermeulen, B. & Goossens, K.G.W. (2010). Debugging multi-core systems-on-chip. In G. Kornaros (Ed.), Multi-Core Embedded Systems. (pp. 155-200) London: CRC Press/Taylor & Francis Group.
Haan, G. de & Braspenning, R. (2010). Video scanning format conversion and motion estimation. In V. Madisetti (Ed.), Video, Speech and Audio Signal Processing and Associated Standards. (pp. 16-1/43) London: CRC Press.
Akesson, K.B., Molnos, A.M., Hansson, M.A., Ambrose, J.A. & Goossens, K.G.W. (2010). Composability and Predictability for Independent Application Development, Verification and Execution. In M. Huebner & J. Becker (Eds.), Multiprocessor System-on-Chip: Hardware Design and Tool Integration. (pp. 25-56) Berlin: Springer.

2009

Otten, R.H.J.M. (2009). Layout synthesis : a retrospective. In Ch.J. Alpert, D.P. Mehta & S.S. Sapatnekar (Eds.), Handbook of algorithms for physical design automation. (pp. 9-29) London: CRC Press.
Shabbir, A., Kumar, Akash, Mesman, B. & Corporaal, H. (2009). Enabling MPSoC design space exploration on FPGAs. In D.M.A. Hussain, A.Q.K. Rajput, B.S. Chowdhry & Q. Gee (Eds.), Wireless networks, information processing and systems : international multi topic conference, IMTIC 2008 Jamshoro, Pakistan, April 11-12, 2008 : revised selected papers. (pp. 412-421) Springer.
Lapalme, J., Theelen, B.D., Stoimenov, N., Voeten, J.P.M., Thiele, L. & Aboulhamid, E.M. (2009). Y-chart based system design: a discussion on approaches. Nouvelles approches pour la conception d'outils CAO pour le domaine des systems embarqu'es. (pp. 23-56) Montreal, Canada: Universite de Montreal.
Punter, H.T., Voeten, J.P.M. & Huang, J. (2009). Quality in model driven engineering. In J. Rech & C. Bunse (Eds.), Model-driven software development : integrating quality assurance. (pp. 37-56) New York: Information Science Reference.

2008

Mousavi, M.R., Reniers, M.A., Basten, A.A. & Chaudron, M.R.V. (2008). PARS : a process algebraic approach to resources and schedulers. In M. Alexander & W. Gardner (Eds.), Process Algebra for Parallel and Distributed Processing. (pp. 331-358) Chapman and Hall.
Funk, M. & Bartneck, C. (2008). An interactive visual canon platform. In P. Ciancarini, R. Nakatsu, M. Rauterberg & M. Roccetti (Eds.), New frontiers for entertainment computing. (pp. 23-32) Berlin: Springer.
Florescu, O., Voeten, J.P.M., Theelen, B.D., Geilen, M.C.W. & Corporaal, H. (2008). Parallel object-oriented specification language. In Alan Burns (Ed.), ARTIST Survey of Programming Languages. s.l.: ARTIST2, Network of Excellence on Embedded System Design.
Meijer, M. & Pineda de Gyvez, J. (2008). Technological boundaries of voltage and frequency scaling for power performance tuning. In A. Wang & S. Naffziger (Eds.), Adaptive Techniques for Dynamic Processor Optimization : Theory and Practice. (pp. 25-47) Berlin: Springer.
Moonen, A.J.M., Bartels, C.L.L., Bekooij, M.J.G., Berg, R.M.J. van den, Bhullar, H., Goossens, K.G.W., Groeneveld, P.R., Huisken, J. & Meerbergen, J. van (2008). Comparison of an Æthereal network on chip and traditional interconnects: two case studies. In G. De Micheli, S. Mir & R. Reis (Eds.), VLSI-SoC: research trends in VLSI and systems on chip : Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2006), October 16 - 18, 2006, Nice, France. (pp. 317-336) Berlin: Springer.
Rijpkema, E., Goossens, K.G.W., Radulescu, A., Dielissen, J., Meerbergen, J. van, Wielage, P. & Waterlander, E. (2008). Trade offs in the design of a router with both guaranteed and best-effort services for netowrks on chip. In R. Lauwerijns & J. Madsen (Eds.), Design Automation, and Test in Europe. The Most Influential Papers of 10 Years DATE, Circuits & Sysems, chapter 2 (Networks on Chip). Springer.

2007

Corporaal, H. (2007). Computerarchitectuur, implementatie en realisatie. In T.M.A. Bemelmans, M. van Keulen, R.J. Kusters & M. Looijen (Eds.), ICT-Zakboek. (pp. 715-781) Amsterdam: Read Business Information.
Corporaal, H. (2007). Embedded systemen en hun ontwerp. In H.S. van Leerdam, R.P. Mertens & A.J.M. Montagne (Eds.), Poly-elektronica zakboek. (pp. D5/12-D5/59) Den Haag: Reed Business Information.
Florescu, O., Voeten, J.P.M., Verhoef, M. & Corporaal, H. (2007). Reusing systems design experience through modelling patterns. In S.A. Huss (Ed.), Advances in Design and Specification Languages for Embedded Systems : Selected Contributions from FDL'06. (pp. 329-348) Dordrecht: Springer.
Moonen, A.J.M., Bartels, C.L.L., Bekooij, M.J.G., Berg, R.M.J. van den, Bhullar, H., Goossens, K.G.W., Groeneveld, P.R., Huisken, J. & Meerbergen, J. van (2007). Comparison of an Aethereal network on chip and traditional interconnects - to case studies. In G. De Micheli, S. Mir & R. Reis (Eds.), VLSI-SoC: Research tgrends on VLSI and Systems on Chip. (pp. 317-336) Springer.

2006

Otten, R.H.J.M. (2006). Design Planning. In L. Scheffer, L. Lavagno & G. Martin (Eds.), EDA for IC system design, verification, and testing. (pp. 14-1/23) London: CRC Taylor & Francis.
Jess, J.A.G. (2006). Core architectures for digital media and the associated compilation techniques. In Ricardo Reis, Marcello Lubaszewski & Jochen A.G. Jess (Eds.), Design of systems on a chip : design and test. (pp. 27-63) Berlin: Springer.
Corporaal, H. (2006). Embedded Systems Design. Progress White Papers 2006. (pp. 7-27) Utrecht: Technologiestichting STW.
Bosch, P.F.A. van den, Florescu, O., Verhoef, M.H.G. & Muller, G.J. (2006). Modeling of performance. In Maurice Heemels & Gerrit Muller (Eds.), Boderc: Model-Based Design of High-Tech Systems: a collaborative research project for multi-disciplinary design analysis of high-tech systems. (pp. 101-113) Eindhoven: Embedded Systems Institute.
Florescu, O., Voeten, J.P.M. & Corporaal, H. (2006). Property-preserving synthesis for unified conrol- and data-oriented models. In Alain Vachoux (Ed.), Applications of Specification and Design Languages for SoCs. (pp. 247-262) Berlin: Springer.
Florescu, O., Voeten, J.P.M. & Corporaal, H. (2006). Model-driven design of real-time systems. In Maurice Heemels & Gerrit Muller (Eds.), Boderc: Model-Based Design of Real-Time Systems: a collaborative research project for multi-disciplinary design analysis of high-tech systems. (pp. 161-170) Eindhoven: Embedded Systems Institute.
Reis, R., Lubaszewski, M. & Jess, J.A.G. (2006). Design of systems on a chip : introduction. In Ricardo Reis, Marcello Lubaszewski & Jochen A.G. Jess (Eds.), Design of systems on a chip : design and test. (pp. 1-7) Berlin: Springer.

2005

Baeten, J.C.M., Mousavi, M.R. & Reniers, M.A. (2005). Timing the untimed : terminating successfully while being conservative. In A. Middeldorp, V. van Oostrom, F. van Raamsdonk & R.C. de Vrijer (Eds.), Processes, Terms and Cycles : Steps on the Road to Infinity, Essays dedicated to Jan Willem Klop on the occasion of his 60th birthday. (pp. 251-279) Berlin: Springer-Verlag.
Goossens, K.G.W., Gonzalez Pestana, S., Dielissen, J.T.M.H., Gangwal, O.P., Meerbergen, J. van, Radulescu, A., Rijpkema, E. & Wielage, P. (2005). Service-based design of systems on chip and networks on chip. In F. Tolenaar & P. van der Stok (Eds.), Dynamic and Robust Streaming Between Connected Consumer-Electronic Devices. (pp. 37-60) Dordrecht: Springer.
Bekooij, M.J.G., Hoes, R.J.H., Moreira, O., Poplavko, P., Pastrnak, M., Mesman, B., Mol, J.J.D., Stuijk, S., Gheorghita, Valentin & Meerbergen, J. van (2005). Dataflow analysis for real-time embedded multiprocessor system design. In P. van der Stok (Ed.), Dynamic and Robust Streaming in and between Connected Consumer-Electronic Devices. (pp. 81-108) Dordrecht: Springer.
Rijpkema, E., Goossens, K.G.W., Radulescu, A., Dielissen, J., Meerbergen, J. van, Wielage, P. & Waterlander, E. (2005). Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. In R. Lauwereins & J. Madsen (Eds.), Design Automation, and Test in Europe. The Most Influential Papers of 10 Years Date. (pp. 125-139) Dordrecht: Springer.

2004

Huang, J., Voeten, J.P.M., Ventevogel, A. & Bokhoven, L.J. van (2004). Platform-independent design for embedded real-time system. In C. Grimm (Ed.), Languages for System Specification. (pp. 35-50) Dordrecht: Kluwer Academic Publishers.

2003

Basten, A.A. (2003). Verifying Petri-net models using process algebra. In C. Girault & R. Valk (Eds.), Petri Nets for Systems Engineering : A Guide to Modeling, Verification and Applications. (pp. 382-397) Berlin: Springer.
Basten, A.A., Geilen, M.C.W., Groot, H. de & Groot, H. de (2003). Omnia Fieri Possent : everything may happen. In A.A. Basten, M.C.W. Geilen & H.W.H. de Groot (Eds.), Ambient Intelligence : Impact on Embedded System Design. (pp. 1-8) Boston: Kluwer Academic.
Meerbergen, J. van (2003). Ambient computing platforms : a Very Large Scale Integration (VLSI) perspective. In E.H.L. Aarts & S. Marzano (Eds.), The new everyday : views on ambient intelligence. (pp. 96-99) Rotterdam: 010 Publishers.
Goossens, K.G.W., Dielissen, J.T.M.H., Meerbergen, J. van, Poplavko, P., Radulescu, A., Rijpkema, E., Waterlander, E. & Wielage, P. (2003). Guaranteeing the quality of services in networks on chip. In A. Jantsch & H. Tenhunen (Eds.), Networks on Chip. (pp. 61-82) Dordrecht: Kluwer Academic Publishers.
Marchal, P., Bruni, D., Gomez, J.I., Benini, L., Pinuel, L., Catthoor, F. & Corporaal, H. (2003). SDRAM-Energy Aware Memory Allocation for Dynamic Multi-Media Applications on Multiprocessor Platforms. In A.A. Jerraya, S. Yoo, N. Wehn & D. Verkest (Eds.), Embedded Software for SoC. (pp. 319-331) Boston, USA: Kluwer Academic Publishers.

2000

Otten, R.H.J.M. (2000). A design flow for performance planning : new paradigms for iteration free synthesis. In E. Börger (Ed.), Architecture design and validation methods. (pp. 89-139) Berlin: Springer.

1999

Corporaal, H. (1999). Algorithm development for scalable processor systems based on transport triggered architectures. In A.B. Smolders & M.P. van Haarlem (Eds.), Perspectives on radio astronomy : technologies for large antenna arrays : proceedings of the conference held at the ASTRON Institute in Dwingeloo on 12-14 April 1999. (pp. 225-234) Haarlem: ASTRON.
Corporaal, H. (1999). Computerarchitectuur, implementatie en realisatie. In P.M.E. De Bra & M. Looijen (Eds.), ICT-zakboekje. (pp. 569-664) Arnhem: Koninklijke PBNA.
Corporaal, H. (1999). Algorithm development for scalable processor systems based on transport triggered architectures. In A.B. Smolders & M.P. van Haarlem (Eds.), Perspectives on Radio Astronomy : Technologies for Large Antenna Arrays. (pp. 225-234) Dwingeloo: ASTRON.

1998

Pineda de Gyvez, J. (1998). Foreword. In G. Manganaro (Ed.), Cellular Neural Networks. Berlin: Springer.
Janssen, G.L.J.M. (1998). Implementation of propositional temporal logics using BDDs. In H. de Swart (Ed.), TABLEAUX, automated reasoning with analytic tableaux and related methods : international conference, 1998, Oisterwijk, The Netherlands, May 5-8, 1998 : proceedings. (pp. 40-41) Berlin: Springer.
Yang, B., Bryant, R.E., O Hallaron, D.R., Biere, A., Coudert, O., Janssen, G.L.J.M., Ranjan, R.K. & Somenzi, F. (1998). A performance study of BDD-based model checking. In G. Gopalakrishnan & P. Windley (Eds.), FMCAD : formal methods in computer-aided design : international conference : proceedings, 2nd, Palo Alto, CA, USA, November 4-6, 1998. (pp. 255-289) Berlin: Springer.

1997

Gerez, S.H., Heemstra de Groot, S.M., Bonsma, E.R. & Heijligers, M.J.M. (1997). Overlapped scheduling techniques for high-level synthesis and multiprocessor realizations of DSP algorithms. In J.C. Lopez, R. Hermida & W. Geisselhardt (Eds.), Advanced Techniques for Embedded System Design and Test. (pp. 125-150) Dordrecht: Kluwer Academic Publishers.
Lombardi, F. & Pineda de Gyvez, J. (1997). Defect tolerance in VLSI systems. In A. Kent & J.G. Williams (Eds.), Encyclopedia of computer science and technology. Basel: Dekker.
Lombardi, F. & Pineda de Gyvez, J. (1997). VLSI Systems, Defect Tolerance. Encyclopedia of Microcomputers. Marcel Dekker.
Theeuwen, J.F.M. (1997). Power reduction through clock gating by symbolic manipulation. In R. Reis & L. Claesen (Eds.), VLS I: Integrated Systems on Silicon. (pp. 389-400) London: Chapman and Hall.

1995

Hilderink, H.A. & Jess, J.A.G. (1995). ROM-based multi thread controller. In G. Saucier & A. Mignotte (Eds.), Logic and Architecture Synthesis : State-of-the-Art and Novel Approaches : IFIP Workshop on Logic and Architecture Synthesis, 1994. (pp. 169-175) London: Chapman and Hall.
Nijssen, R.X.T. & Jess, J.A.G. (1995). Datapath regularity extraction. In G. Saucier & A. Mignotte (Eds.), Logic and Architecture Synthesis : State-of-the-Art and Novel Approaches : IFIP Workshop on Logic and Architecture Synthesis, 1994. (pp. 151-157) London: Chapman and Hall.
Theeuwen, J.F.M. (1995). Module generators and their integration in an architectural synthesis system. In G. Saucier & A. Mignotte (Eds.), Logic and Architecture Synthesis : State-of-the-Art and Novel Approaches : IFIP Workshop on Logic and Architecture Synthesis, 1994. (pp. 245-251) London: Chapman and Hall.

1990

Pineda de Gyvez, J. & Jess, J.A.G. (1990). Systematic extraction of critical areas from IC layouts. In C.H. Stapper, V.K. Jain & G. Saucier (Eds.), Defect and Fault Tolerance in VLSI System. (Volume 3). New York: Plenum press.

1989

Janssen, J.G.M., Schoenmakers, P.J. & Cramers, C.A.M.G. (1989). A fundamental study of the effects of modifiers in supercritical fluid chromatography. In P. Sandra (Ed.), Proceedings of the 10th International Symposium on Capillary Chromatography. (pp. 1383-1396) Heidelberg: Huthig.

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Conference proceeding

2012

Goossens, S.L.M., Kouters, K., Akesson, K.B. & Goossens, K.G.W. (2012). Memory-map selection for firm real-time SDRAM controllers. Proceedings of 2011 Design, Automation and Test in Europe Conference and Exhibition, DATE '11, 14-18 March 2011, Dresden, Germany. (pp. 1-4). Piscataway: IEEE Service Center.
Yang, Yang, Geilen, M.C.W., Basten, A.A., Stuijk, S. & Corporaal, H. (2012). Playing games with scenario- and resource-aware SDF graphs through policy iteration. Proceedings of the Design, Automation and Test in Europe 2012, 12-16 March 2012, Dresden, Germany. EDAA.

2011

Voeten, J.P.M., Hendriks, T., Theelen, B.D., Schuddemat, J., Tabingh Suermondt, W., Gemei, J., Kotterink, K. & Huet, J. van (2011). Predicting timing performance of advanced mechatronics control systems. In G. Eichler, A. Kuepper, V. Schau, H. Fouchal & H. Unger (Eds.), Proceedings of Computer Software and Applications Conference Workshops COMPSACW, 18-22 July 2011, Munich, Germany. (pp. 206-210). Piscataway: IEEE Service Center.
Stuijk, S., Geilen, M.C.W., Theelen, B.D. & Basten, A.A. (2011). Scenario-aware dataflow : modeling, analysis and implementation of dynamic applications. In L. Carro & A.D. Pimentel (Eds.), Proceedings of the 11th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 18-21 July 2011, Samos, Greece. (pp. 404-411). Piscataway: IEEE Service Center.
Stuijk, S., Basten, A.A., Akesson, K.B., Geilen, M.C.W., Moreira, O. & Reineke, J. (2011). Designing next-generation real-time streaming systems : tutorial. Proceedings of the 9th International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS,9-14 October 2011, Taipei, Taiwan. (pp. 375-376). Piscataway: IEEE Service Center.
Braak, G.J.W. van den, Nugteren, C., Mesman, B. & Corporaal, H. (2011). Fast Hough Transform on GPUs : Exploration of Algorithm Trade-Offs. In Jacques Blanc-Talon, Richard Kleihorst, Wilfried Philips, Dan Popescu & Paul Scheunders (Eds.), Proceedings of ACIVS'11 : Advanced Concepts for Intelligent Vision systems, 22-25 August 2011, Heidelberg, Germany. (pp. 611-622). Berlin: Springer.
Rooijakkers, M.J., Rabotti, C., Bennebroek, M., Meerbergen, J. van & Mischi, M. (2011). Low-complexity R-peak detection in ECG signals: A preliminary step towards ambulatory fetal monitoring. Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2011), 30 August - 3 September 2011,
Steine, M., Geilen, M.C.W. & Basten, A.A. (2011). Distributed maintenance of minimum-cost path information in wireless sensor networks. 6th ACM workshop on Performance Monitoring and Measurement of Heterogeneous Wireless and Wired Networks, 31 October 2011, Maimi, Florida. (pp. 25-32). New York: ACM Press.
Steine, M., Viet Ngo, Cuong, Serna Oliver, R., Geilen, M.C.W., Basten, A.A., Fohler, G. & Decotignie, J.D. (2011). Proactive reconfiguration of wireless sensor networks. 14th ACM International Confernce on Modeling, Analysis and Simulation of Wireless and Mobile Systems, 31 october - 4 November 2011, Maimi Beach, Florida. (pp. 31-40). New York: ACM Press.
Trcka, N., Hendriks, M., Basten, A.A., Geilen, M.C.W. & Somers, L.J.A.M. (2011). Integrated model-driven design-space exploration for embedded systems. Proceedings of the 11th International Conference Embedded Computer Systems (SAMOS 2011, Samos, Greece, July 18-21, 2011). (pp. 339-346). IEEE.
Trcka, N., Voorhoeve, M. & Basten, A.A. (2011). Parameterized partial orders for modeling embedded system use cases : formal definition and translation to coloured Petri nets. Proceedings of the 11th International Conference on Application of Concurrency to System Design (ACSD'11, Kanazawa, Japan, June 2-24, 2011). (pp. 13-18). Los Alamitos: IEEE Computer Society.
Kumar, Akash, Fernando, S.D. & Manoharan, Manmohan (2011). Bringing soccer to the field of real-time embedded systems education. In J. Jackson, P. Marwedel & K. Ricks (Eds.), Proceedings of the 6th Workshop on Embedded Systems Education, WESE '11. (pp. 46-52). New York: ACM.
Goossens, S.L.M., Akesson, K.B. & Goossens, K.G.W. (2011). Reconfiguration of a predictable and composable SDRAM conroller with persistent applications. Proceedings Annual Workshop on PROGram for Research on Embedded Systems & Software (Progress'11).
Nugteren, C. & Corporaal, H. (2011). Using performance prediction to enable architectural choice prior to the development of target specific code. Proceedings of the 16th Using performance prediction to enable architectural choice prior to the development of target specific code, 14-15 November 2011, Veldhoven, The Netherlands. Utrecht: STW.
Nugteren, C., Braak, G.J.W. van den, Corporaal, H. & Mesman, B. (2011). High performance predictable histogramming on GPUs : exploring and evaluating algorithm trade-offs. Proceedings of the Fourth Workshop on General Purpose Processing on Graphics Processing Units (GPGPU) at ASPLOS'11. 5 March 2011, Newport Beach, California. New York: ACM.
He, Y., Ye, Z., She, D., Mesman, B. & Corporaal, H. (2011). Feasibility analysis of ultra high frame rate visual servoing on FPGA and SIMD processor. Proceedings of the Advanced Concepts for Intelligent Vision Systems (ACIVS'11), 22-25 August 2011, Ghent, Belgium. (pp. 623-634). Berlin: Springer.
He, Y., She, D., Mesman, B. & Corporaal, H. (2011). MOVE-Pro: a low power and high code density TTA architecture. Proceedings of the 11th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 18-21 July 2011, Samos, Greece. (pp. 294-301). Piscataway: IEEE Service Center.
Ye, Z., Corporaal, H. & Jonker, P.P. (2011). PhD forum: A cyber-physical system approach to embedded visual servoing. Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras (ICDSC), 22-25 August 2011, Ghent, Belgium. (pp. 1-2). Piscataway: IEEE Service Center.
Ye, Z., He, Y., Pieters, R.S., Mesman, B., Corporaal, H. & Jonker, P.P. (2011). Bottlenecks and Tradeoffs in high frame rate visual servoing : a case study. Proceedings of the IAPR Conference on Machine Vision Applications (MVA), 13-15 June 2011, Nara Centennial Hall, Nara, Japan. Piscataway: IEEE.
Ye, Z., He, Y., Pieters, R.S., Mesman, B., Corporaal, H. & Jonker, P.P. (2011). Demo : an embedded vision system for high frame rate visual servoing. Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras (ICDSC), 22-25 August 2011, Ghent, Belgium. (pp. 1-2). Piscataway: IEEE Service Center.
Ye, Z., He, Y., Pieters, R., Mesman, B. & Corporaal, H. (2011). Bottlenecks and tradeoffs in ultra high frame rate isual servoing : a case study. Proceedings of the 12th IAPR Conference on Machine Vision Applications (MVA'11), 13-15 June 2011, Nara, Japan. (pp. 55-58).
Peemen, M.C.J., Mesman, B. & Corporaal, H. (2011). Efficiency optimization of trainable feature extractors for a consumer platform. Proceedings of ACIVS'11 : Advanced Concepts for Intelligent Vision systems, 22-25 August 2011, Ghent, Belgium. (Lecture Notes in Computer Science, Vol. 6915, pp. 293-304). Berlin: Springer.
Peemen, M.C.J., Mesman, B. & Corporaal, H. (2011). Speed sign detection and recognition by convolutional neural networks. Proceedings of the 8th International Automotive Congress, May 16-17, 2011, Eindhoven, The Netherlands. (pp. 162-170).
Liu, B., Pourshaghaghi, H.R., Moreno Londono, S. & Pineda de Gyvez, J. (2011). Process variation reduction for CMOS logic operating at sub-threshold supply voltage. Proceedings of the 2011 14th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD), 31 August - 2 September 2011, Oulu, Finland. (pp. 135-139). Piscataway: IEEE Service Center.
She, D., He, Y., Mesman, B. & Corporaal, H. (2011). Energy efficient code generation for processors with exposed datapath. Proceedings of the 9th workshop on Optimizations for DSP and Embedded Systems (ODES'11), 2 April 2011, Chamonix, France. (pp. 55-61).
Siyoum, F.M., Geilen, M.C.W., Moreira, O., Nas, R.J.M. & Corporaal, H. (2011). Analyzing synchronous dataflow scenariaos for dynamic software-defined radio applications. Proceedings of the International Symposium on System-on-Chip (SOC 2011), 31 October - 2 November 2011, Tampere, Finland. (pp. 14-21). Piscataway: IEEE Service Center.
Siyoum, F.M., Akesson, K.B., Stuijk, S., Goossens, K.G.W. & Corporaal, H. (2011). Resource-efficient real-time scheduling using credit-controlled static-priority arbitration. Proceedings of the International Conference on Embedded an Real-Time Computing Systems and Applications, RTCSA 11, 28-31 August 2011, Toyama. (pp. 309-318). Los Alamitos, USA: IEEE Computer Society Press.
Yang, Yang, Geilen, M.C.W., Basten, A.A., Stuijk, S. & Corporaal, H. (2011). Iteration-based trade-off analysis of resource-aware SDF. In P. Kitsos (Ed.), Proceedings of the 14th Euromicro Conference on Digital System Design (DSD), 31 August - 2 September 2011, Oulu, Finland. (pp. 567-574). Los Alamitos: IEEE Computer Society Press.
Shabbir, A., Stuijk, S., Kumar, Akash, Corporaal, H. & Mesman, B. (2011). An MPSoC design approach for multiple use-cases of throughput constrained applications. Proceedings of the 8th ACM International Conference on Computing Frontiers, CF '11, 3-5 May 2011, Ischia, Italy. (pp. 1-2). New York, USA: ACM Press.
Shabbir, A., Kumar, Akash, Mesman, B. & Corporaal, H. (2011). Distributed resource management for concurrent execution of multimaedia applications on MPSoC platforms. In L. Carro & A.D. Pimentel (Eds.), Proceedings of the IEEE International Symposium on Embedded Computer Systems (IC-SAMOS 2011), 18-21 July 2011, (pp. 132-139). Piscataway: IEEE.
Nabi, M., Geilen, M.C.W. & Basten, A.A. (2011). MoBAN : configurable mobility model for wireless body area networks. Proceedings of the 4th International ICST Conference on Simulation Tools and Techniques (SIMUTools 2011), March 21-25, Barcelona, Spain. Brussels, Belgium: ICST.
Nabi, M., Geilen, M.C.W. & Basten, A.A. (2011). MoBAN: a configurable mobility model for wireless body area networks. Proceedings of the 4th International Conference on Simulation Tools and Techniques (SIMUTools 2011), 21-25 March 2011, Barcelona, Spain. (pp. 168-177). Brussels, Belgium: ICST.
Nabi, M., Blagojevic, M., Geilen, M.C.W. & Basten, A.A. (2011). Dynamic data prioritization for quality-of-service differentiation in heterogeneous wireless sensor networks. Proceedings of the 8th IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks (SECON 2011), June 27-30 2011, Salt Lake City, Utah, USA. (pp. 217-225). Washington DC, USA: IEEE Communication Society Press.
Nabi, M., Blagojevic, M., Geilen, M.C.W. & Basten, A.A. (2011). Dynamic data prioritization for quality-of-service differentiation in heterogeneous wireless sensor networks. Proceedings of the 8th Annual IEEE Communication Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks (SECON 2011), 27-30 June 2011, Salk Lake City, Utah. (pp. 296-304). Piscataway: IEEE Service Center.
Mirzoyan, D., Akesson, K.B. & Goossens, K.G.W. (2011). Impact of application quality parameters on the application throughput and output quality in MPSoCs. Proceedings of Annual Workshop on PROGram for Research on Embedded Systems & Software (Progress'11).
Blagojevic, M., Nabi, M., Geilen, M.C.W., Basten, A.A., Hendriks, T. & Steine, M. (2011). A probabilistic acknowledgment mechanism for wireless sensor networks. Proceedings of the 2011 6th IEEE International Conference on Networking, Architecture and Storage (NAS), 28-30 July 2011, Dalian, Liaoning. (pp. 63-72). Washington D.C.: IEEE Computer Society Press.
Damavandpeyma, M., Stuijk, S., Basten, A.A., Geilen, M.C.W. & Corporaal, H. (2011). Hybrid code-data prefetch-aware multiprocessor task graph scheduling. In Paris Kitsos (Ed.), Proceedings of the 2011 14th Euromicro Conference on Digital System Design, 31 August - 2 September , 2011, Oulu, Finland. (pp. 583-590). Los Alamitos: IEEE Computer Society Press.
Diken, E., Jordans, R., Corvino, R., Jozwiak, L. & Lindwer, M. (2011). Automated architecture synthesis and application mapping for ASIP based adaptable MPSoCs. Proceedings of the 7th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2011), 10-16 July 2011, Fiuggi, Italy. (pp. 135-138). Ghent, Belgium: Academia Press.
Solon Nery, A., Jozwiak, L., Lindwer, M., Cocco, M., Nedjah, N. & Franca, F.M.G. (2011). Hardware reuse in modern application-specific processors and accelerators. Proceedings of the 14th Euromicro Conference on Digital System Design (DSD 2011), 31 August - 2 September 2011, Rio de Janeiro, Brazil. (pp. 140-147). Los Alamitos: IEEE Computer Society Press.
Solon Nery, A., Nedjah, N., Felipe, M.G.F. & Jozwiak, L. (2011). A parallel architecture for ray-racing with an embedded intersection algorithm. Proceedings of the 2011 International Symposium on Circuits and Systems (ISCAS 2011), 15-18 May 2011, Rio de Janeiro, Brazil. (pp. 1491-1494). Los Alamitos, USA: IEEE Computer Society Press.
Solon Nery, A., Nedjah, N., Franca, F.M.G. & Jozwiak, L. (2011). A parallel ray tracing architecture suitable for application-specific hardware and GPGPU implementations. Proceedings of the 14th Euromicro Conference on Digital System Design 2001 (DSD2011), 31 August - 2 September 2011, Oulu, Finland. (pp. 511-518). Piscataway: IEEE.
Solon Nery, A., Nedjah, N., Franca, F.M.G. & Jozwiak, L. (2011). Massively parallel identification of intersection points for GPGPU ray tracing. In Y. Xiang, W. Zhou, A. Cuzzocrea & M. Hobbs (Eds.), ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part II. (pp. 14-23). Berlin: Springer Verlag.
Corvino, R., Gamatie, A. & Boulet, P. (2011). Efficient task fusion exploration for data intensive computing SoC. Proceedings of ICT.open 2011, 14-15 November 2011, Veldhoven. STW.
Gomony, M.D., Akesson, K.B. & Goossens, K.G.W. (2011). A parallel-access method for 3D-stacked DRAMs. Proceedings of Annual Workshop on PROGram for Research on Embedded Systems & Software (Progress'11).
Chandrasekar, K., Akesson, K.B. & Goossens, K.G.W. (2011). Improved power modeling of DDR SDRAMs. Proceedings of the 14th Euromicro Conference on Digital System Design 2001 (DSD2011), 31-02 September 2011, Oulu, Finland. (pp. 99-108). Piscataway: IEEE.
Chandrasekar, K., Akesson, K.B. & Goossens, K.G.W. (2011). Predictable power-down policies for SDRAMs. Proceedings of the Annual Workshop on PROGram for Research on Embedded Systems & Software (Progress'11).
Akesson, K.B. & Goossens, K.G.W. (2011). Architectures and modeling of predictable memory controllers for improved system integration. Proceedings of the Design, Automation & Test in Europe Converence & Exhibition (EDAA), 14-18 March 2011, Grenoble, France. (pp. 1-6). Grenoble, France.
Akesson, K.B., Hayes, W. & Goossens, K.G.W. (2011). Automatic generation of efficient predictable memory patterns. Proceedings of the 17th International Conference on Embedded and Real-Time Computing Systems and Applications 2011. (pp. 177-184). Piscataway: IEEE.
Akesson, K.B., Huang, Po-Chun, Clermidy, F., Dutoit, D., Goossens, K.G.W., Chang, Yuan-Hao, Kuo, Tei-Wei, Vivet, P. & Wingard, D. (2011). Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends. Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis 2011 (CODES+ISSS), 09-14 Oktober 2011, Taipei, Taiwan. (pp. 3-12). Taipei, Taiwan.
Azevedo, A., Vermeulen, H.G.H. & Goossens, K.G.W. (2011). Architecture of the event distribution network for cross-triggering debug. Proceedings of the Annual Workshop on PROGram for Research on Embedded Systems & Software (Progress'22).
Bensalem, S,, Goossens, K.G.W., Kirsch, C.M., Obermaisser, R., Lee, E.A. & Sifakis, J. (2011). Time-predictable and composable architectures for dependable embedded systems. Proceedings of the International Conference on Embedded Software (EMSOFT'11), 9-4 October 2011, Taipei, Taiwan. Taipei, Taiwan.
Gomez Agis, F., Hu, H., Luo, J., Mulvad, H.C.H., Galili, M., Calabretta, N., Oxenløwe, L.K., Dorren, H.J.S. & Jeppesen, P. (2011). Optical switching and detection of 640 Gb/s OTDM data packets transmitted over 50 km of fiber. Proceedings of the 37th European Conference on Optical Communication (ECOC 2011), 18 - 22 September 2011, Geneva, Switzerland. (pp. 1-3). Piscataway: IEEE Service Center.
Hendriks, M., Geilen, M.C.W. & Basten, A.A. (2011). Pareto analysis with uncertainty. Proceedings of the 9th IFIP International Conference on Embedded and Ubiquitous Computing, EUC 2011, 24-26 October 2011, Melbourne, Australia. (pp. 189-196). Los Alamitos: IEEE Computer Society Press.
Koedam, M., Stuijk, S. & Corporaal, H. (2011). Exploiting inter and intra application dynamism to save energy. In P. Kitsos (Ed.), Proceedings of the 14th Euromicro Conference on Digital System Design (DSD), 31 August - 2 September 2011, Oulu, Finland. (pp. 708-715). Los Alamitos: IEEE Computer Society Press.
Lokhorst, C., Hogewerf, P.H., Mol, R.M. de, Verhoeven, R., Steine, M., Lukkien, J.J. & Bennebroek, M. (2011). Wireless sensor application for dairy cow activity monitoring. Proceedings of the 5th European Conference on Precision Livestock Farming, 11-14 July 2011, Prague, Czech Republic. (pp. 17-26). Prague: Czech Centre for Science and Society.
Moreno Londono, S. & Pineda de Gyvez, J. (2011). Exploration analysis of process variation sensitivity in risc-like microprocessors operating at low supply voltages. Proceedings of the 2011 Subthreshold Microelelectronics Conference, 26-27 September 2011, Lexington, Massachusetts.
Nejad, A.B., Escudero Martinez, M. & Goossens, K.G.W. (2011). An FPGA bridge preserving traffing quality of service for on-chip network-based systems. Proceedings of 2011 Design, Automation and Test in Europe Conference and Exhibition, DATE '11, 14-18 March 2011, Dresden, Germany. (pp. 1-6). Piscataway: IEEE Service Center.
Nejad, A.B., Molnos, A.M. & Goossens, K.G.W. (2011). Enabling time-triggered scheduling on a composable embedded system. Proceedings of the Annual Workshop on PROGram for Research on Embedded Systems & Software (Progress'22).
Nelson, A.T., Molnos, A.M. & Goossens, K.G.W. (2011). Composable power management with energy and power budgets per application. Proceedings of the 2011 International Conference on Embedded Computer Systems (SAMOS), 18-21 July 2011. (pp. 396-403). Piscataway: IEEE Service Center.
Nelson, A.T., Molnos, A.M. & Goossens, K.G.W. (2011). A desing concept for independent multi-application development. Proceedings of Annual Workshop on PROGram for Research on Embedded Systems & Software (Progress'11).
Nelson, A.T., Moreira, O., Molnos, A.M., Stuijk, S., Nguyen, B.T. & Goossens, K.G.W. (2011). Power minimisation for real-time dataflow applications. In P. Kitsos (Ed.), Proceedings of the 14th Euromicro Conference on Digital System Design (DSD), 31 August - 2 September 2011, Oulu, Finland. (pp. 117-124). Los Alamitos: IEEE Computer Society Press.
Schenkelaars, T., Vermeulen, H.G.H. & Goossens, K.G.W. (2011). Optimal scheduling of switched flexray networks. Proceedings of 2011 Design, Automation and Test in Europe Conference and Exhibition, DATE '11, 14-18 March 2011, Dresden, Germany. (pp. 1-6). Piscataway: IEEE Service Center.
Singh, A.K., Kumar, Akash & Srikanthan, Th. (2011). A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs. Proceedings of the 14th IEEE International Conference on Compilers Architectures and Synthesis for Embedded Systems (CASES), October 9-14, 2011,Taipei, Taiwan. (pp. 175-184). ACM/IEEE.
Singh, A.K., Kumar, Akash & Srikanthan, Th. (2011). A design space exploration methodology for application specific MPSoC design. Proceedings of the2011 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2011), 4-6 July 2011, Chennai, India. (pp. 339-340). Piscataway: IEEE.
Stefan, R.A. & Goossens, K.G.W. (2011). Enhancing the security of time-divition-multiplexing networks-on-chip through the use of multipath routing. Proceedings of the 4th International Workshop on Network on Chip Architectures 2011, (NoCArc '11), December 4-5, 2011, Porto Alegre, Brazil. (pp. 57-62). New York, USA: ACM.
Stefan, R.A. & Goossens, K.G.W. (2011). An improved algorithm for slot selection in the AEthereal network-on-chip. Proceedings of Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OMC 2011).
Stefan, R.A. & Goossens, K.G.W. (2011). Run-time allocation in contention-free routing NoCs. Proceedings of the Annual Workshop on PROGram for Research on Embedded Sysems & Software (Progress'11), 20-23 september 2011, Lodz, Poland.
Teeselink, E., Somers, L.J.A.M., Basten, A.A., Trcka, N. & Hendriks, M. (2011). A visual language for modeling and analyzing printer data path architectures. Proceedings of Industrial Track of Software Language Engineering 2011 (ITSLE 2011), 5 July 2011, Braga, Portugal. (pp. 1-20).
Theelen, B.D., Geilen, M.C.W. & Voeten, J.P.M. (2011). Performance Model Checking Scenario-Aware Dataflow. In S. Tripakis U. Fahrenberg (Ed.), Proceedings of the 9th international conference on formal modeling and analysis of timed systems (FORMATS). (pp. 43-59). Berlin: Springer.
Wahlah, M.A. & Goossens, K.G.W. (2011). PUMA Placement unification with mapping and guaranteed throughput allocation on FPGA using a hardwired NoC. Proceedings of the Euromicro Symposium on Digital System Design (DSD'11), 31 August - 2 September 2011, Oulu, Finland. (pp. 88-96). Piscataway: IEEE Service Center.
Wahlah, M.A. & Goossens, K.G.W. (2011). A non-intrusive online FPGA test scheme using a hardwired network on chip. Proceedings of the Euromicro Symposium on Digital System Design (DSD'11), 31 August - 2 September 2011, Oulu, Finland. (pp. 351-359). Piscataway: IEEE Service Center.
Zaykov, P.G., Molnos, A.M., Kuzmanov, G. & Goossens, K.G.W. (2011). Communication of slack availability with timestamps in multiprocessor systems. Proceedings of the Annual Workshop on PROGram for Research on Embedded Sysems & Software (Progress'11), 20-23 september 2011, Lodz, Poland.
Zjajo, A. & Pineda de Gyvez, J. (2011). A 1.2V 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOS. International Symposium on Low Power Electronics and Design, ISLPED 2011, 1-3 August 2011, Fukuoka, Japan. (pp. 187-192). Piscataway: IEEE Service Center.

2010

Jozwiak, L. & Jan, Y. (2010). Design of hardware accelerators for demanding applications. Proceedings of the IEEE Latin American Symposium on Circuits and Systems, LASCAS 2010, 24-26 February 2010, Iguascu Falls, Brasil. (pp. 252-255). Piscataway: IEEE Service Center.
Jozwiak, L. & Jan, Y. (2010). Quality-driven methodology for demanding accelarator design. proc. of the IEEE Int. Conf. on Quality Electronic Design 2010, ISQUED 2010, 22-24 March 2010, San Jose, USA. (pp. 380-389). Los Alamitos: IEEE Computer Society Press.
Jozwiak, L. & Jan, Y. (2010). Architecture design of reconfigurable accelerators for demanding apllications. Proc. Int. COnf. on Information Technology: New Generations ITNG 2010, Las Vegas, USA, 12-14 April 2010. (pp. 1201-1206). Los Alamitos: IEEE Computer Society Press.
Vermeulen, H.G.H. & Goossens, K.G.W. (2010). Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks. Workshop on High-Level Desitgn Validation and Test (HLDVT). (pp. 1-8).
Geilen, M.C.W. & Stuijk, S. (2010). Worst-case performance analysis of synchronous dataflow scenarios. Proceedings of the International Conference on Hardware-Software Codesign and System Synthesis, CODE+ISSS 10, 24-29 October 2010, Scottsdale, Arizona. (pp. 125-134). New York: ACM Press.
Stuijk, S., Geilen, M.C.W. & Basten, A.A. (2010). A predictable multiprocessor desgin flow for streaming applications with dynamic behaviour. Proceedings of the 2010 13th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD), 1-3 September 2010, Lille, France. (pp. 548-555). Los Alamitos: IEEE Computer Society Press.
Vermeulen, B. & Goossens, K.G.W. (2010). Debugging multi-core systems-on-chip. In G. Kornaros (Ed.), Multi-core embedded systems : proceedings of European Test Symposium, ETS, May 2010. (pp. 155-200). CRC Press.
Sidorova, N., Stahl, C. & Trcka, N. (2010). Workflow soundness revisited : checking correctness in the presence of data while staying conceptual. In B. Pernici (Ed.), Advanced Information Systems Engineering (22nd International Conference, CAiSE 2010, Hammamet, Tunisia, June 7-9, 2010. Proceedings). (Lecture Notes in Computer Science, Vol. 6051, pp. 530-544). Berlin: Springer.
Basten, A.A., Geilen, M.C.W., Haverkort, B.R., Hendriks, T. & Stuijk, S. (2010). Dependable sensor and actuator networks. Proceedings of Technology and Research Roadmap for IIP Sensor Networks, Position Papers, 24-28 August 2010. Enschede, The Netherlands. (pp. 27-28). Z.pl.: Z.Uitg..
Basten, A.A., Benthum, E. van, Geilen, M.C.W., Hendriks, M., Houben, F., Igna, G., Reckers, F.J., Smet, S. de, Somers, L.J.A.M., Teeselink, E., Trcka, N., Vaandrager, F.W., Verriet, J.H., Voorhoeve, M. & Yang, Yang (2010). Model-driven design-space exploration for embedded systems: the Octopus Toolset. In T. Margaria & B. Steffen (Eds.), Proceedings Leveraging Applications of Formal Methods, Verification, and Validation, Prt I,4th International Symposium, ISoLA 2010, Heraklion, Crete, Greece, October 18-20, 2010. (Lecture Notes in Computer Science, Vol. 6415, pp. 90-105). Berlin: Springer.
Braak, G.J.W. van den, Mesman, B. & Corporaal, H. (2010). Compile-time GPU memory access optimizations. In F.J. Kurdahi & J. Takala (Eds.), Proceedings of the 2010 International Conference on Embedded Computer Systems (SAMOS), 19-22 July , 2010, Samos Greece. (pp. 200-207). Piscataway: IEEE Service Center.
Trcka, N. (2010). Workflow data footprints. In W. Abramowicz & R. Tolksdorf (Eds.), Business Information Systems (13th International Conference, BIS 2010, Berlin, Germany, May 3-5, 2010. Proceedings). (Lecture Notes in Business Information Processing, Vol. 47, pp. 218-229). Berlin: Springer.
Vosters, L.P.J., Haan, G. de & Peset, R. (2010). Specialized depth extraction for live soccer. Proceedings of 21st ProRISC Workshop of the STW.ICT Conference, 18-19 November 2010, Veldhoven, The Netherlands. (pp. 1-31). Utrecht: STW.
He, Y., Ye, Z., She, D., Pieters, R.S., Mesman, B. & Corporaal, H. (2010). 1000 fps visual servoing on the reconfigurable wide SIMD processor. In T. Kielmann, M.J. van Kreveld & W.J. Niessen (Eds.), Proceedings of the 16th Annual Conference of the Advanced School for Computing and Imgaging 2010 (ASCI 2010), 1-3 November 2010, Veldhoven, The Netherlands. (pp. 302-309).
He, Y., Pu, Y., Moreno Londono, S., Kleihorst, R.P., Abbo, A.A. & Corporaal, H. (2010). Xetal-Pro : an ultra-low energy and high throughput SIMD processor. Proceedings of the 47th ACM/EEE int. conference on design automation DAC'10. (pp. 543-548).
Ye, Z., Pieters, R.S., Mesman, B., Corporaal, H. & Jonker, P.P. (2010). FPGA Implementation of 1000 fps visual servoing for repetitive structures. proceedings of the first STW.ICT conference on Research in Information and Communication Technology 18-19 November 2010 Veldhoven, The Netherlands. Veldhoven: STW. Poster.
Yang, Yang, Geilen, M.C.W., Basten, A.A., Stuijk, S. & Corporaal, H. (2010). Automated bottleneck-driven design-space exploration of media processing sysems. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE) 2010, 8-12 March 2010, Dresden, Germany. (pp. 1041-1046). Los Alamitos: IEEE Computer Society Press.
Yang, Yang, Geilen, M.C.W., Basten, A.A., Stuijk, S. & Corporaal, H. (2010). Automated bottleneck-driven design-space exploration of media processing systems. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE) 2010, 8-12 March 2010, Dresden, Germany. (pp. 1041-1046). Los Alamitos: IEEE Computer Society Press.
Shabbir, A., Stuijk, S., Kumar, Akash, Theelen, B.D., Mesman, B. & Corporaal, H. (2010). A predictable communication assist. Proceedings of the International Conference on Computing Frontiers, CF 2010, 17-19 May 2010, Bertinoro, Italy. (pp. 97-98). New York: ACM Press.
Jan, Y. & Jozwiak, L. (2010). Architecture exploration of re-configurable hardware accelerators for highly-demonding applications. Proceedings of 21st ProRISC Workshop of the STW.ICT Conference, 18-19 November 2010, Veldhoven, The Netherlands. (pp. 1-2). Utrecht: STW.
Nabi, M., Basten, A.A., Geilen, M.C.W., Blagojevic, M. & Hendriks, T. (2010). A robust protocol stack for multi-hop wireless body area networks with transmit power adaptation. Proceedings of the 5th International Conference on Body Area Networks, Bodynets 2010, September 10-12, 2010, Corfu Island, Greece. (pp. 1-7). New York: ACM press.
Nabi, M., Blagojevic, M., Geilen, M.C.W., Basten, A.A. & Hendriks, T. (2010). MCMAC: an optimized medium access control protocol for mobile clusters in wireless sensor networks. Proceedings of the 2010 7th Annual IEEE Communications Society Conference on Sensor Mesh and Ad Hoc Communications and Networks (SECON), 21-25 June 2010, Boston, Massachussetts. (pp. 28-36). Piscataway: IEEE Service Center.
Pourshaghaghi, H.R. & Pineda de Gyvez, J. (2010). Adaptive voltage (frequency) scaling based on fuzzy logic controllers. Proceedings of ProRISC 2009, 20th Annual Workshop on Circuits Systems and Signal Processing, November 26-27, 2009, Veldhoven, The Netherlands. (pp. 263-268). Utrecht: STW Technology Foundation.
Pourshaghaghi, H.R. & Pineda de Gyvez, J. (2010). Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling. Proceedings of the 17th IEEE Int. Conference on Electronics, Circuits and Systems (ICECS 2010) December 12-15 2010, Athens.
Maatta, T.T., Harma, A. & Aghajan, H. (2010). On efficient use of multi-view data for activity recognition. Proceedings of the 4th ACM/IEEE International Conference on Distributed Smart Cameras, 31 August - 4 September 2010, Atlanta, Georgia. (pp. 1-8). ACM.
Mirzoyan, D., Akesson, K.B. & Goossens, K.G.W. (2010). Impact of proces variations on the throughput of real-time applications in multiprocessor system-on-chip. Annual Workshop on PROGram for Research on Embedded Systems & Software (Progress). Utrecht: STW Foundation.
Heinrich, A., Bartels, C.L.L., Vleuten, R.J. van der & Haan, G. de (2010). Robust motion estimation design methodology. Proceedings of the 2010 Conference on Visual Media Production (CVMP), 17-18 November 2010. (pp. 49-57). Piscataway: IEEE Service Center.
Goossens, K.G.W. & Hansson, M.A. (2010). The aethereal network on chip after ten years: Goals, evolution, lessons and future. Proc. Design Automation Conference (DAC), 2010 47th ACM/IEEE, Anaheim, CA, 13-18 June 2010. (pp. 306-3011).
Goossens, K.G.W., She, D., Milutinović, A. & Molnos, A.M. (2010). Composable dynamic voltage and frequency scaling and power management for dataflow applications. Proceedings of the 2010 13th Euromicro Conference on Digital System Design : Architectures, Methods and Tools (DSD), 1-3 September 2010, Lille, France. (pp. 107-114). Los Alamitos: IEEE Computer Society Press.
Damavandpeyma, M., Stuijk, S., Basten, A.A., Geilen, M.C.W. & Corporaal, H. (2010). Thermal-aware scratchpad memory design and allocation. Proceedings of the 2010 IEEE International Conference on Computer Design (ICCD), 3-6 October 2010, Amsterdam, The Netherlands. (pp. 118-124). Los Alamitos: IEEE Computer Society Press.
Damavandpeyma, M., Stuijk, S., Basten, A.A., Geilen, M.C.W. & Corporaal, H. (2010). DMA-aware scheduling for multiprocessor systems-on-chip. proc. of PROGRESS 2010, Annual Workshop . Utrecht: STW.
Damavandpeyma, M., Stuijk, S., Basten, A.A., Geilen, M.C.W. & Corporaal, H. (2010). Thermal-aware address decoding in scratchpad memories. Proceedings of the 6th International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, ACACES 2010, 11-17July 2010, Terrassa, Spain. (pp. 197-198). Ghent: HiPEAC.
Akesson, K.B., Hayes Jr., W. & Goossens, K.G.W. (2010). Classification and analysis of predictable memory patterns. Proceedings of the 16th IEEE International Conference on Embedded and Real-time Computing Systems and Applications, RTCSA 2010, 23-25 August 2010, Macau, Sar, China. (pp. 367-376). Piscataway: IEEE Service Center.
Baloukas, C., Papadopoulos, L., Soudris, D., Stuijk, S., Jovanovic, O., Schmoll, F., Cordes, D., Pyka, A., Mallik, A., Mamagkakis, S., Capman, F., Collet, S., Mitas, N. & Kritharidis, D. (2010). Mapping embedded applications on MPSoCs : the MNEMEE approach. Proceedings of the 2010 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 5-7 July 2010, Lixouri, Kefalonia, Greece. (pp. 512-517). Los Alamitos: IEEE Computer Society Press.
Chandrasekar, K., Akesson, K.B. & Goossens, K.G.W. (2010). Modeling and optimizing power for a real-time SDRAM controller. Proc. of Annual workshop on PROGress. Utrecht: STW Foundation.
Drijvers, T., Alba Pinto, C.A., Corporaal, H., Mesman, B. & Braak, G.J.W. van den (2010). Fast Huffman decoding by exploiting data level parallelism. In F.J. Kurdahi & J. Takala (Eds.), Proceedings of the 2010 International Conference on Embedded Computer Systems (SAMOS), 19-22 July , 2010, Samos Greece. (pp. 86-92). Piscataway: IEEE Service Center.
Larsson, E., Vermeulen, H.G.H. & Goossens, K.G.W. (2010). A distributed architecture to check global properties for post-silicon debug. Proceedings of the 15th IEEE European Test Symposium (ETS), 24-28 May 2010. (pp. 182-187). Piscataway: IEEE Service Center.
Larsson, E., Vermeulen, B. & Goossens, K.G.W. (2010). A distributed architecture to check global properties for post silicon-debug. Proceedings of the 2010 15th IEEE European Test Symposium (ETS), 24-28 May 2010, Praha, Czechia. (pp. 182-187). Piscataway: IEEE Service Center.
Larsson, E., Vermeulen, B. & Goossens, K.G.W. (2010). Checking pipelined disributed global properties for post-silicon debug. Proceedings of the IEEE Eleventh Workshop on RTL and High Level Testing (WRTLT'10), 5-6 December 2010, Shanghai, China. (pp. 1-6). Piscataway: IEEE Service Center.
Meijer, M. & Pineda de Gyvez, J. (2010). Body bias driven design synthesis for optimum performance per area. Proceedings of the 2010 11th International Symposium on Quality Electronic Design (ISQED), 22-24 March 2010, San Jose, California. (pp. 472-477). Piscataway: IEEE Service Center.
Meijer, M., Pineda de Gyvez, J., Kup, B., Uden, B. van, Bastiaansen, P., Lammers, M. & Vertregt, M. (2010). A forward body bias generator for digital CMOS circuits with supply voltage scaling. Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 - June 2, 2010, Paris, France. (pp. 2482-2485). Piscataway: IEEE Service Center.
Mhamdi, L., Goossens, K.G.W. & Senin, I.V. (2010). Buffered crossbar fabrics based on networks on chip. Proceedings of the 2010 Eight Annual Communication Networks and Services Research Conference (CNSR), 11-14 May 2010, Montreal, Canada. (pp. 74-79). Piscataway: IEEE Service Center.
Molnos, A.M., Ambrose, J.A., Nelson, A., Stefan, R., Cotofana, S. & Goossens, K.G.W. (2010). A composable, energy-managed, real-time MPSOC platform. Proceedings of the 2010 12th International Conference on Optimization of Electrical and Electronic Equipment (OPTIM), 20-22 May 2010, Basov. (pp. 870-876). Piscataway: IEEE Service Center.
Molnos, A.M., Milutinović, A., She, D. & Goossens, K.G.W. (2010). Composable processor virtualization for embedded systems. Proceedings of the Workshop on Computer Architecture and Operating System Co-Design (CAOS). (Lecture Notes in Computer Science). Springer.
Molnos, A.M., Milutinović, A., She, D. & Goossens, K.G.W. (2010). Composable processor virtualization for embedded sysems. Workshop on Computer Architecture and Operating System Co-Design (CAOS). (Lecture Notes in Computer Science, pp. 1-10). Springer.
Moreno Londono, S. & Pineda de Gyvez, J. (2010). Extending Amdahl's law for energy-efficiency. Proceedings of the First Annual International Conference on Energy Aware Computing, (ICEAC 2010), December 16-18, 2010, Cairo.
Moreno Londono, S., Pourshaghaghi, H.R. & Pineda de Gyvez, J. (2010). Dynamic voltage scaling for an adaptive energy-aware 32-bit multiplier based on fuzzy logic controller. Proceedings of of PRORISC 2010, 21st Annual Workshop on Circuits Systems and Signal Processing, Veldhoven.
Nejad, A.B., Martinez, M.E. & Goossens, K.G.W. (2010). On-chip interconnect protocol stack exploration for FPGA board-to-board bridging.18-19-11-2010, Veldhoven. Proceedings of the Annual Workshop on Circuits, Systems and Signal Processing (ProRISC), 18-19 November 2010, Veldhoven, The Netherlands. Utrecht: STW.
Nejad, A.B., Martinez, M.E. & Goossens, K.G.W. (2010). On-chip interconnect protocol stack exploration for FPGA board-to-board bridging. proc. Annual Workshop on PROGress. Utrecht: STW Foundation.
Nelson, A., Moreira, O., Stuijk, S., Molnos, A.M., Goossens, K.G.W. & Nguyen, Thang (2010). Ideas on power minimisation for real-time dataflow applications through voltage & freuency scaling. Proc. of Annual Workshop on Circuits, systems and singal processing (ProRisc). Utrecht: STW Foundation.
Oceguera, A., Basten, A.A., Somers, L.J.A.M. & Hulsenboom, S. (2010). Real-time step motor emulation for Hardware-in-the-Loop simulation. 42nd Summer Computer Simulation Conference, SCSC 2010. (pp. 306-313).
Pastrnak, M., With, P.H.N. de & Meerbergen, J. van (2010). Real-time aware rendering of scalable arbitrary-shaped MPEG-4 decoder for multiprocessor systems. Proceedings Real-Time Image Processing, 29-30 January, 2007, San Jose, California. (Proceedings of SPIE, Vol. 6496, pp. 6496 0D-1-6496 0D-9). Bellingham: SPIE.
Poplavko, P., Geilen, M.C.W. & Basten, A.A. (2010). Predicting the throughput of multiprocessor applications under dynamic workload. Proceedings of the 2010 IEEE International Conference on Computer Design (ICCD), 3-6 October 2010, Amsterdam, The Netherlands. (pp. 282-288). Los Alamitos: IEEE Computer Society Press.
Shojaei, H., Wu, T.-H., Davoodi, A. & Basten, A.A. (2010). A pareto-algebraic framework for signal power optimization in global routing. Proceedings of the 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 18-20 August 2010, Austin, Texas. (pp. 407-412). Piscataway: IEEE Service Center.
Singh, A.K., Kumar, Akash, Srikanthan, Th. & Ha, Y. (2010). Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA. Proceedings of the 2010 International Conference on Field-programmable Technology (FPT'10), 8-10 December 2010, Bejing, China. (pp. 365-368). Piscataway: IEEE Service Center.
Singh, A.K., Jigang, W., Kumar, Akash & Srikanthan, Th. (2010). Run-time mappig of multiple communicating tasks on MPSoC platforms. Proceedings of the International Conference on Computational Science, ICCS 2010, 31 May - 2 June 2010, Amsterdam, The Netherlands. (pp. 1019-1026). Amsterdam: Elsevier.
Stefan, R., Windt, J. de & Goossens, K.G.W. (2010). On-chip network interfaces supporting automatic burst write creation, posted writes and read prefetch. Proceedings of the 2010 International Conference on Embedded Computer Systems (SAMOS), 19-22 July , 2010, Samos Greece. (pp. 185-192). Piscataway: IEEE Service Center.
Wiggers, M.H., Bekooij, M.J.G., Geilen, M.C.W. & Basten, A.A. (2010). Simultaneous budget and buffer size computation for throughput-constrained task graphs. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE) 2010, 8-12 March 2010, Dresden, Germany. (pp. 1669-1672). Los Alamitos: IEEE Computer Society Press.
Xing, J., Theelen, B.D., Langerak, R., Pol, J.C. van de, Tretmans, J. & Voeten, J.P.M. (2010). UPPAAL in practice : quantitative verification of a RapidIO network. In T. Margaria & B. Steffen (Eds.), Proceedings of the 4th International Symposium on Leveraging Applications of Formal Methods, Verification and Validation, ISoLA 2010, October 18-21, 2010, Heraklion, Greece. (pp. 160-174). Berlin: Springer.
Xing, J., Theelen, B.D., Langerak, R., Pol, J.C. van de, Tretmans, J. & Voeten, J.P.M. (2010). From POOSL to UPPAAL : transformation and quantitative analysis. Proceedings of the 10th International Conference on Application of Concurrency to System Design (ACSD 2010), 21-25 June 2010, Braga, Portugal. (pp. 47-56). Los Alamitos: IEEE Computer Society.
Yang, Z.J., Kumar, Akash & Ha, Y. (2010). An area-efficient dynamically reconfigurable spatial division multiplexing network-onchip with static throughput guarantee. proc. of the int. confernce on field-programmable technology. Los alamitos: IEEE.
Zjajo, A. & Pineda de Gyvez, J. (2010). An adaptive digital caliration of multi-step A/D converters. Proceedings of the 2010 IEEE 10th International Conference on Signal Processing (ICSP), 24-28 October 2010, Beijing, China. (pp. 2456-2459). Piscataway: IEEE Service Center.

2009

Geilen, M.C.W. (2009). Reduction techniques for synchronous dataflow graphs. Proceedings of the 46th ACM/IEEE Design Automation Conference 2009, DAC'09, 26-31 July 2009, San Francisco, California. (pp. 911-916). Piscataway: IEEE.
Brombacher, A.C., Funk, M., Karapanos, E., Koca, A. & Rozinat, A. (2009). Analyzing quality of innovative products with uncertain specifications. Proceedings of the 9th Annual Meeting of ENBIS (European Network for Business and Industrial Statistics). Göteborg, Sweden. Abstract.
Bartels, C.L.L. & Haan, G. de (2009). Temporal symmetry constraints in block-matching. Proceedings of the 13th IEEE international symposium on Consumer electronics, 25-28 May 2009, Kyoto, Japan. (pp. 749-750). Piscataway: IEEE Service Center.
Bartels, C.L.L. & Haan, G. de (2009). Occlusion classifiers for picture rate conversion. In Majid Rabbani (Ed.), Visual communications and image processing 2009 : 20 - 22 January 2009, San Jose, California, USA ; proceedings IS&T/SPIE electronic imaging, science and technology. (pp. 7257-59). Bellingham: SPIE.
Mischi, M., Rabotti, C., Vosters, L.P.J., Oei, S.G. & Bergmans, J.W.M. (2009). Electrohysterographic conduction velocity estimation. Proceedings of the 31st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2009, 2-6 September 2009. Minneapolis, Minnesota. (pp. 6934-6939). Piscataway: IEEE.
Steine, M., Bekooij, M.J.G. & Wiggers, M. (2009). A priority-based budget scheduler with conservative dataflow model. In A. Nunez & P.P. Carballo (Eds.), Proceedings 12th Euromicro Conference on Digital System Design, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece. (pp. 37-44). Los Alamitos: IEEE Computer Society Press.
Funk, M., Hoyer, P. & Link, S. (2009). Model-driven Instrumentation of graphical user interfaces. Proceedings of the 2nd Internatinal Conference on Advances in Computer-Human Interactions, ACHI'09, 1-7 February 2009, Cancun, Mexico. (pp. 19-25). Washington: IEEE Computer Society.
Funk, M., Putten, P.H.A. van der & Corporaal, H. (2009). Analytics for the internet of things. CHI 2009 - digital life, new world : conference proceedings and extended abstracts ; the 27th Annual CHI Conference on Human Factors in Computing Systems, April 4 - 9, 2009 in Boston, USA. (pp. 4195-4200). New York: ACM Press.
Funk, M., Rozinat, A., Alves De Medeiros, A.K., Putten, P.H.A. van der, Corporaal, H. & Aalst, W.M.P. van der (2009). Improving product usage monitoring and analysis with semantic concepts. In Jianhua Yang & Athula Ginige (Eds.), Information systems: modeling, development, and integration (Third International United Information Systems Conference UNISCON 2009, Sydney, Australia, April 21-24, 2009. Proceedings). (Lecture Notes in Business Information Processing, Vol. 20, pp. 190-201). Berlin: Springer.
Roozeboom, F., Bergveld, H.J., Nowak, K., LeCornec, F., Guiraud, L., Bunel, C., Iochem, S., Ferreira, J., Ledain, S., Pieraerts, E. & Pommier, M. (2009). Ultrahigh-density trench capacitors in silicon and their application to integrated DC-DC conversion. Proc. 23th Eurosensors Conf., Lausanne, Sept. 16-19, 2009. (pp. 426). Invited paper.
Roozeboom, F., Bergveld, H.J., Nowak, K., LeCornec, F., Guiraud, L., Bunel, C., Iochem, S., Ferreira, J., Ledain, S., Pieraerts, E. & Pommier, M. (2009). Ultrahigh-density trench cpacitors in silicon and their application to integrated DC-DC conversion. Proc. Eurosensors XXIII (Procedia Chemistry), Lausanne, 06-09 Sept. 2009, (pp. 1435-1438).
Yang, Yang, Geilen, M.C.W., Basten, A.A., Stuijk, S. & Corporaal, H. (2009). Exploring tradeoffs between performance and resource requirements for synchronous dataflow graphs. Proceedings of 7th IEEE/ACM/IFIP workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2009, 15-16 October 2009, Grenoble, France. (pp. 96-105). Piscataway: IEEE.
Shabbir, A., Kumar, Akash, Mesman, B. & Corporaal, H. (2009). Performance evaluation of concurrently executing parallel applications on multi-processor system. Proceedings of the International Symposium on Systems, Architectures, Modeling ans Simulation (SAMOS '09) 20-23 July 2009, Greece. (pp. 100-107). Piscataway, NJ: IEEE.
Jan, Y. & Jozwiak, L. (2009). Survey of advanced CABAC accelarator architectures for future multimedia. In J. Becker, R. Woods & P. Athanas (Eds.), Proceedings 5th international workshop on Reconfigurable computing architectures, tools and applications, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. (Lecture Notes in Computer Science, Vol. 5453, pp. 342-348). Springer.
Jan, Y. & Jozwiak, L. (2009). CABAC accelerator architectures for video compression in future multimedida : a survey. In K. Bertels, N. Dimopoulos & C.R. Silvano (Eds.), Proceedings 9th international workshop on Embedded computer systems : architectures, modeling, and simulation, SAMOS 2009, July 20-23, 2009, Samos, Greece. (Lecture Notes in Computer Science, Vol. 5657, pp. 24-35). Berlin: Springer.
Nabi, M., Blagojevic, M., Basten, A.A., Geilen, M.C.W. & Hendriks, T. (2009). Exploring a WSN design space using genetic algorithms. Proceedings of 5th International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, ACACES'09. 12-15 July 2009, Ghent, Belgium. (pp. 327-328). Ghent: HiPEAC.
Nabi, M., Blagojevic, M., Basten, A.A., Geilen, M.C.W. & Hendriks, T. (2009). Configuring multi-objective evulutionary algorithms for design-space exploration of wireless sensor networks. Proceedings of 4th ACM International Workshop on Performance Monitoring, Measurement and Evaluation of Heterogeneous Wireless and Wired Networks, PM2HW2N 2009, 26 October 2009, tenerife, spain. (pp. 111-119). New York: ACM.
Pourshaghaghi, H.R. & Pineda de Gyvez, J. (2009). Dynamic voltage scaling based on supply current tracking using fuzzy logic controller. Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, 13-16 December 2009, Yasmine Hammamet, Tunesia. (pp. 779-782). Piscataway: IEEE Service Center.
Pourshaghaghi, H.R., Ahmadi, R. & Jahed-Motlagh, M.R. (2009). Reconfigurable logic blocks based on a discrete chaotic circuit : implementation of all fundamental two input, one output logic functions. Proceedings of the Second IFAC Conference on Analysis and Control of Chaotic Systems, 22-24 June 2009, London, United Kingdom. (pp. 1-6). Oxford: Pergamon.
Maatta, T.T., Härmä, A. & Aghajan, H. (2009). Home-to-home communication using 3D shadows. Proceedings of the 2nd International Conference on Immersive Telecommunications, IMMERSCOM 2009, 27-29 May 2009, Berkeley, CA. (pp. 20-1-6). New York: ACM.
Blagojevic, M., Nabi, M., Hendriks, T., Basten, A.A. & Geilen, M.C.W. (2009). Fast simulation methods to predict wireless sensor network performance. In A. Boukerche, I. Guerin-Lassous & S. Olariu (Eds.), Proceedings of the 6th ACM international symposium on Performance Evaluation of Wireless Ad Hoc, Sensor and Ubiquitous Networks, PE-WASUN 2009, 26-30 October 2009, Tenerife, Spain. (pp. 41-48). New York: ACM.
Bergveld, H.J., Nowak, K., Karadi, R., Iochem, S., Ferreira, J., Ledain, S., Pieraerts, E. & Pommier, M. (2009). A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration. Proc. IEEE Energy Conversion Congress and Exposition (ECCE'09), San Jose, USA, 20-24 Sept. 2009. (pp. 3698-3705). Piscataway: IEEE.
Akesson, K.B., Hansson, M.A. & Goossens, K.G.W. (2009). Composable resource sharing based on latency-rate servers. Proceedings of the 12th Euromicro conference on Digital system design, 27-29 August 2009, Paras, Greece. (pp. 547-555). Los Alamitos: IEEE Computer Society.
Akesson, K.B., Steffens, E.F.M. & Goossens, K.G.W. (2009). Efficient service allocation in hardware using credit-controlled static-priority arbitration. 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009, 24 - 26 August 2009, Beijing. (pp. 59-68). Piscataway: IEEE Service Center.
An, L., Heinrich, A., Cordes, C.N. & Haan, G. de (2009). Improved picture rate conversion using classification based LMS-filters. In Majid Rabbani (Ed.), Visual communications and image processing 2009 : 20 - 22 January 2009, San Jose, California, USA ; proceedings IS&T/SPIE electronic imaging, science and technology. (pp. 7257-56). Bellingham: SPIE.
Bartneck, C., Funk, M. & Bhomer, M. ten (2009). Dancing with myself : the interactive visual canon platform. 27th International Conference on Human Factors in Computing Systems (CHI2009) 04-04-09-04-2009. (pp. 3501-3502). Boston: ACM.
Cordes, C.N. & Haan, G. de (2009). Key requirements for high quality picture-rate conversion. Digest of SID'09, 31 May - 5 June 2009, San Antonio, Texas. (pp. 57.1-1-4).
Groothuis, M., Frijns, R.M.W., Voeten, J.P.M. & Broenink, J. (2009). Concurrent Design of Embedded Control Software. Proceedings of the 3rd International Workshop on Multi-Paradigm Modeling. (Electronic Communications of the EASST, Vol. 21)., submitted / in press.
Hansson, M.A. & Goossens, K.G.W. (2009). An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. Embedded Systems Week 2009, ESWEEK 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009, 11 - 16 October 2009, Grenoble. (pp. 99-108). New York: ACM.
Hansson, M.A., Subburaman, M. & Goossens, K.G.W. (2009). aelite: A flit-synchronous network on chip with composable and predictable services. Proceedings of 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, 20 - 24 April 2009, Nice, France. (pp. 250-255). Piscataway: IEEE Service Center.
Hoes, R.J.H., Basten, A.A., Yeow, W.-L., Tham, C.K., Geilen, M.C.W. & Corporaal, H. (2009). QoS management for wireless sensor networks with a mobile sink. In U. Roedig & C.J. Sreenan (Eds.), Proceedings of the 6th European conference on Wireless sensor networks, EWSN 2009, February 11-13, 2009,Cork, Ireland. (Lecture Notes in Computer Science, Vol. 5432, pp. 53-68). Berlin: Springer.
Hu, H. & Haan, G. de (2009). Class-count reduction techniques for content adaptive filtering. Proceedings of the 13th IEEE International Symposium on Consumer Electronics, ISCE'09, 25-28 May 2009, Kyoto, Japan. (pp. 11-15). Piscataway: IEEE.
Meijer, M., Liu, B., Veen, R. van & Pineda de Gyvez, J. (2009). Post-silicon tuning capabilities of 45nm low-power CMOS digital circuits. Proceedings of 2009 Symposium on VLSI Circuits, 16-18 June 2009, Honolulu, Hawaii. (pp. 110-111). Piscataway: IEEE.
Moreno Londono, S. & Pineda de Gyvez, J. (2009). An energy-aware multiplier based on a configurable-reuse of points design methodology. Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, 13-16 December 2009, Yasmine Hammamet, Tunesia. Piscataway: IEEE Service Center, submitted / in press.
Moreno Londono, S. & Pineda de Gyvez, J. (2009). Energy aware systems design methodologies : overview and proposal for an energy-aware multiplier implementation. Proceedings of PRORISC 2009. Veldhoven: STW, submitted / in press.
Ophelders, F.E.B., Bekooij, M.J.G. & Corporaal, H. (2009). A tuneable software cache coherence protocol for heterogeneous MPSoCs. Embedded Systems Week 2009, ESWEEK 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009, 11 October - 16 October 2009, Grenoble. (pp. 383-392). New York: ACM.
Pu, Y., Pineda de Gyvez, J., Corporaal, H. & Ha, Y. (2009). An ulra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply. Proceedings of the IEEE International Solid-State Circuits Conference 2009, ISSCC 2009, 8-12 February 2009, San Francisco, CA, USA. (pp. 146-147a). Piscataway: IEEE.
Rong, J., Gritti, T. & Shan, C. (2009). Upscaling faces for recognition systems using trained filters. Proceedings of the 2009 ACM Multimedia Conference & co-located workshops : October 19 - 24, 2009, Beijing, China. (pp. 105-112). New York: ACM Press.
Shojaei, H., Ghamarian, A.H., Basten, A.A., Geilen, M.C.W., Stuijk, S. & Hoes, R.J.H. (2009). A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management. Proceedings of the 46th ACM/IEEE Design Automation Conference 2009, DAC'09, 26-31 July 2009, San Francisco, CA,USA. (pp. 917-922). Piscataway: IEEE.
Smit, G.J.M., Hoeven, G.F. van der, Groote, J.F., Otten, R.H.J.M., Tonino, J.F.M., Juurlink, B.H.H. & Haverkort, B.R.H.M. (2009). The 3TU Embedded Systems Masters in the Netherlands. In P. Marwedel, J. Jackson & K. Ricks (Eds.), Proceedings of the 2009 Workshop on Embedded Systems Education (Grenoble, France, October 15, 2009). (pp. 8-12). New York: ACM.
Wang, J., Haan, G. de, Unay, D., Soldea, O. & Ekin, A. (2009). Voxel-based discriminant map classification on brain ventricles for Alzheimer's disease. In J.P.W. Pluim (Ed.), Progress in Biomedical Optics and Imaging, Medical Imaging : Image Processing, 8-10 February 2009, Lake Buena Vista, Florida, USA. (Proceedings of SPIE, Vol. 7259, pp. 67-69). Bellingham: SPIE.

2008

Frijns, R.M.W., Fatemi, S.H., Mesman, B. & Corporaal, H. (2008). DC-SIMD: dynamic communication for SIMD processors. Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium. (pp. 1-10).
Bartels, C.L.L. & Haan, G. de (2008). Smoothnes constraints in Motion Estimation [niet openbaar]
Kumar, Akash & Berkel, C.H. van (2008). Vectorization of Reed Solomon decoding and mapping on the EVP. Proceedings 11th Design, Automation and Test in Europe - Conference and Exhibition (DATE'08, Munich, Germany, March 10-14, 2008). (pp. 450-455). Leuven: EDAA.
Koca, A., Funk, M., Karapanos, E., Rozinat, A. & Gaarden, N. van der (2008). Grasping product pragmatics: a case with internet on tv. In J. Masthoff, S. Panabaker, M. Sullivan & A. Lugmayr (Eds.), 1st International Conference on Designing Interactive User Experiences for TV and Video, Silicon Valley, California, USA , October 22 - 24, 2008. (ACM International Conference Proceeding Series, Vol. 291, pp. 193-201). New York: ACM.
He, Y., Deen, N.G., Sint Annaland, M. van & Kuipers, J.A.M. (2008). Gas-solid turbulent flow in a circulating fluidized bed riser, numerical study of binary particle mixtures. Proceedings of the 9th International Conference on Circulating Fluidized Beds (CFB-9), 13-16 May 2008, Hamburg, Germany.
He, Y., Deen, N.G., Sint Annaland, M. van & Kuipers, J.A.M. (2008). Gas-solid turbulent flow in a circulating fluidized beds riser: numerical study of binary particle mixtures. Proceedings of the 9th International Conference on Circulating Fluidized Beds, 13-16 May 2008, Hamburg, Germany.
He, Y., Zivkovic, Z., Kleihorst, R.P., Danilin, A. & Corporaal, H. (2008). Real-time implementations of Hough transform on SIMD architecture. Second ACM/IEEE International Conference on Distributed Smart Cameras, 2008 : ICDSC 2008 ; 7 - 11 Sept. 2008, Stanford University, [Palo Alto, CA] (pp. 1-8). Piscataway: IEEE.
He, Y., Zivkovic, Z., Kleihorst, R.P., Danilin, A., Corporaal, H. & Mesman, B. (2008). Real-time hough transform on 1-D SIMD processors: implementation and architecture exploration. In Jacques Blanc-Talon, Salah Bourennane & Wilfried Philips (Eds.), Advanced concepts for intelligent vision systems : 10th international conference, ACIVS 2008, Juan-les-Pins, France, October 20-24, 2008 ; proceedings. (Lecture Notes in Computer Science, Vol. 5259, pp. 254-255). Berlin: Springer.
Funk, M., Nijssen, A. & Lichter, H. (2008). From UML to ANSI-C. An Eclipse-Based Code Generation Framework. Proceedings of the Third International Conference on Software and Data Technologies : Porto, Portugal, July 5 - 8, 2008. Setubal: INSTICC.
Funk, M., Putten, P.H.A. van der & Corporaal, H. (2008). UML profile for modeling product observation. FDL 2008. Forum on Specification, Verification and Design Languages, 2008, 23-25 September 2008, Stuttgart, Germany. (pp. 185-190). Los Alamitos: IEEE Computer Society.
Funk, M., Putten, P.H.A. van der & Corporaal, H. (2008). Model interpretation for executable observation specifications. Proceedings of the Twentieth International Conference on Software Engineering and Knowledge Engineering : San Francisco, USA, July 1 - 3, 2008. (pp. 785-790). Skokie: Knowledge Systems Institute Graduate School.
Funk, M., Putten, P.H.A. van der & Corporaal, H. (2008). Specification for user modeling with self-observing systems. The First International Conference on Advances in Computer-Human Interaction (ACHI 2008) : February 10 - 15, 2008, Sainte Luce, Martinique. (pp. 243-248). Los Alamitos: IEEE Computer Society.
Heinrich, A., Haan, G. de & Cordes, C.N. (2008). A Novel performance measure for picture rate conversion methods. Digest of technical papers / International Conference on Consumer Electronics, 2008, ICCE 2008 : 9 - 13 Jan. 2008, Las Vegas, NV. (pp. 8.3-1-1-2). Piscataway: IEEE.
Bergveld, H.J., Karadi, R. & Nowak, K. (2008). An inductive down converter system-in-package for integrated power management in battery-powered applications. Proc. IEEE Power Electronics Specialist Conference (PESC 2008, Rhodes, 15-19 June 2008). (pp. 3335-3341). Piscataway: IEEE.
Akesson, K.B., Steffens, E.F.M., Strooisma, E. & Goossens, K.G.W. (2008). Real-time scheduling using credit-controlled static-priority arbitration. 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications : RTCSA '08 : 25 - 27 Aug. 2008, Kaohsiung, Taiwan. (pp. 3-14). Piscataway: IEEE.
Ghamarian, A.H., Geilen, M.C.W., Basten, A.A. & Stuijk, S. (2008). Parametric throughput analysis of synchronous data flow graphs. In D. Sciuto & Z. Peng (Eds.), Design, automation and test in Europe, 2008 : DATE '08 ; Munich, Germany, 10 - 14 March 2008. (pp. 116-121). Piscataway: IEEE Service Center.
Hansson, M.A., Akesson, K.B. & Meerbergen, J. van (2008). Multi-processor programming in the embedded system curriculum. Proceedings of the Workshop on Embedded Systems Education (WESE) 2008, October 23rd, 2008, Atlanta, Georgia. (pp. 1-9).
Hansson, M.A., Wiggers, M., Moonen, A.J.M., Goossens, K.G.W. & Bekooij, M.J.G. (2008). Applying dataflow analysis to dimension buffers for guaranteed performance in networks on chip. 2nd ACM/IEProceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chips (NOCS 2008) 7 - 11 April 2008, Newcastle upon Tyne, UK. (pp. 211-212). Piscataway: IEEE.
Hartel, P.H., Ruys, T.C. & Geilen, M.C.W. (2008). Scheduling optimisations for SPIN to minimise buffer requirements in synchronous data flow. In A. Cimatti & R.B. Jons (Eds.), Formal Methods in Computer-Aided Design, 2008. FMCAD '08, 17-20 November 2008. (pp. 1-10). Los Alamitos: IEEE Computer Society.
Huang, J., Voeten, J.P.M., Wolfs, S. & Coopmans, M. (2008). An executable interface specification for industrial embedded system design. The Eighth International Conference on Quality Software, 2008 : QSIC '08 ; 12 - 13 Aug. 2008, Oxford, UK ; proceedings ; [in conjunction with] the Third International Workshop on Integration of Software Engineering and Agent Technologies (ISEAT 2008). (pp. 37-44). Piscataway: IEEE.
Igna, G., Kannan, V., Yang, Yang, Basten, A.A., Geilen, M.C.W., Vaandrager, F.W., Voorhoeve, M., Smet, S. de & Somers, L.J.A.M. (2008). Formal modeling and scheduling of datapaths of digital document printers. In F. Cassez & C. Jard (Eds.), Formal Modeling and Analysis of Timed Systems (6th International Conference, FORMATS 2008, Saint Malo, France, September 15 - 17, 2008. Proceedings). (Lecture Notes in Computer Science, Vol. 5215, pp. 170-187). Berlin: Springer.
Mamagkakis, S., Lemmens, P., Soudris, D., Basten, A.A., Marwedel, P., Kritharidis, D. & Guilmin, G. (2008). MNEMEE: Memory managment technology for adaptive and efficient design of embedded systems. Proceedings of 16th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, 13-15 October 2008, Rhodes Island, Greece. (pp. 341-342). Los Alamitos: IEEE Computer Society Press.
Moonen, A.J.M., Bekooij, M.J.G., Berg, R.M.J. van den & Meerbergen, J. van (2008). Cache aware mapping of streaming apllications on a multiprocessor system-on-chip. In D. Sciuto & Z. Peng (Eds.), Design, automation and test in Europe, 2008 : DATE '08 ; Munich, Germany, 10 - 14 March 2008. (pp. 300-305). Piscataway: IEEE Service Center.
Ophelders, F.E.B., Chakraborty, S. & Corporaal, H. (2008). Intra- and inter-processor hybrid performance modeling for MPS0C architectures. Proceedings ot the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis. (pp. 91-96).
Pu, Y., Pineda de Gyvez, J., Corporaal, H. & Ha, Y. (2008). Statistical noise margin estimation for sub-threshold combinational circuits. Proceedings of ASPDAC 2008. (pp. 176-179).
Shao, L., Wang, J., Kirenko, I. & Haan, G. de (2008). Quality adaptive trained filters for compression artifacts removal. Acoustics, Speech and Signal Processing, 2008. ICASSP 2008. IEEE International Conference, March 31 2008-April 4 2008. (pp. 89-900).
Shojaei, H., Basten, A.A., Geilen, M.C.W. & Stanley-Marbell, P. (2008). SPaC: A symbolic Pareto Calculator. Proceedings of the International Conference on Hardware-Software Codesign and System Synthesis, CODES+ISSS 2008. (pp. 179-184). s.l.: ACM.
Theelen, B.D. (2008). Performance Model Generation for MPSoC Design-Sapce Exploration. Quantitative Evaluation of Systems,proceedings of the 5th International Conference on the Quantitative Evaluation of Systems, St. Malo (Fr.) 14-17 Sept. 2008. (pp. 39-40). Los Alamitos: IEEE Computer Society.
Wang, J., Ekin, A. & Haan, G. de (2008). Shape analysis of brain ventricles for improved classification of Alzheimers's patients. IEEE Benelux Signal Processing Symposium, proceedings, Hilvarenbeek, Netherlands, April 2004. (pp. 2252-2255). Piscataway: IEEE.
Zjajo, A. & Pineda de Gyvez, J. (2008). DfT for full accessibility of multi-step analog to digital converters. VLSI Design, Automation and Test 2008, VLSI-DAT. IEEE International Symposium, 23-25-04-2008. (pp. 73-76).
Zjajo, A. & Pineda de Gyvez, J. (2008). Calibration and Debugging of Multi-Step Analog to Digital Converters. Electronic Design, Test and Applications 2008, DELTA 2008, 4th International Symposium, 23-25-01-2008. (pp. 512-515). Piscataway: IEEE.
Zjajo, A. & Pineda de Gyvez, J. (2008). Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. Design, Automation and Test in Europe Conference 2008, DATE 2008, Proceedings, 10-14-03-2008. (pp. 74-79).
Zjajo, A., Krishnan, S. & Pineda de Gyvez, J. (2008). Efficient estimation of die-level process parameter variations via the EM-algorithm. Design and Diagnostics of Electronic Circuits and Systems 2008, DDECS 2008, 11th IEEE Workshop 16-18-04-2008. (pp. 1-16).

2007

Geilen, M.C.W. & Basten, A.A. (2007). A Calculator for Pareto Points. Proceedings of the 10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007) 16-20 April 2007, Nice, France. (pp. 285-291). Piscataway, New Jersey: IEEE Service Center.
Stuijk, S., Basten, A.A., Geilen, M.C.W. & Corporaal, H. (2007). Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs. Proceedings of the 44th Design Automation Conference (DAC 2007) 4-8 June 2007, San Diego, California, USA. (pp. 777-782). ACM Press.
Bartels, C.L.L. & Haan, G. de (2007). Direct Motion Estimation in the Radon Transform Domain using Match-profile Backprojections. Proceedings of the IEEE International Conference on Image Processing 2007 (ICIP 2007), 16-19 September 2007, San Antonio, Texas, USA. (pp. 153-156). San Antonio.
Haan, G. de (2007). Television Display Processing: Past & Future. Digest of the ICCE. (pp. 53-54). Las Vegas.
Kumar, Akash, Mesman, B., Corporaal, H., Theelen, B.D. & Ha, Y. (2007). A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-Featured Media Devices. Proceedings of the 44th Design Automation Conference (DAC 2007) 4-8 June 2007, San Diego, California, USA. (pp. 726-731). ACM Press.
Kumar, Akash, Fernando, S.D., Ha, Y., Mesman, B. & Corporaal, H. (2007). Multi-processor system-level synthesis for multiple applications on platform FPGA. In Koen Bertels (Ed.), International Conference on Field Programmable Logic and Applications, 2007 : FPL 2007 ; 27 - 29 Aug. 2007, Amsterdam, The Netherlands. (pp. 92-97). Piscataway: IEEE Operations Center.
Kumar, Akash, Hansson, M.A., Huisken, J. & Corporaal, H. (2007). An FPGA design flow for reconfigurable network-based multi-processor systems on chip. Design, Automation & Test in Europe Conference & Exhibition, 2007 : DATE '07 ; 16 - 20 April 2007, [Nice, France] (pp. 1-6). Piscataway: IEEE Service Center.
Aa, T. van der, Jayapala, M., Corporaal, H., Catthoor, F. & Deconinck, G. (2007). Impact of ILP-improving code transformations on loop buffer energy. 11th Workshop on Interaction between Compilers and Computer Architecture 2007 : INTERACT 11 ; February 11, 2007, Phoenix, Arizona, USA. (pp. 8-15). Red Hook: Curran.
Akesson, K.B., Goossens, K.G.W. & Ringhofer, M. (2007). Predator: a Predictable SDRAM Memory Controller. Proc. of the 5th IEEE/ACM international conference on Hardware/Software co-design and system synthesis. (pp. 251-256). New York: ACM.
Brand, J.W. van den, Ciordas, C., Goossens, K.G.W. & Basten, A.A. (2007). Congestion-controlled Best-Effort Communication for Networks-on-Chip. Proceedings of the 10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007) 16-20 April 2007, Nice, France. (pp. 984-953). Piscataway, New Jersey: IEEE Service Center.
Ghamarian, A.H., Stuijk, S., Basten, A.A., Geilen, M.C.W. & Theelen, B.D. (2007). Latency Minimization for Synchronous Data Flow Graphs. Proceedings of the 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) 29-31 August 2007, Lübeck, Germany. (pp. 189-196). Los Alamitos, California, USA: IEEE Computer Society.
Hansson, M.A., Coenen, M.J. & Goossens, K.G.W. (2007). Reducing latency by sharing time slots in time-multiplexed networks on chip. Proc. of Int. Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). (pp. 149-154). ACM.
Hansson, M.A., Coenen, M. & Goossens, K.G.W. (2007). Channel trees: Reducing latency by sharing time slots in time-multiplexed networks on chip. CODES+ISSS 2007: 5th International Conference on Hardware/Software Codesign and System Synthesis, 30 September 2007 through 3 October 2007, Salzburg. (pp. 149-154).
Hansson, M.A., Coenen, M. & Goossens, K.G.W. (2007). Trade-offs in the configuration of a network on chip for multiple use-cases. 2007 Design, Automation and Test in Europe Conference and Exhibition, 16 April 2007 through 20 April 2007, Nice Acropolis. (pp. 954-959).
Hansson, M.A., Coenen, M. & Goossens, K.G.W. (2007). Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. Proceedings of Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07, 16-20 April 2007, San Jose, California. (pp. 954-959). Piscataway: IEEE Service Center.
Hoes, R.J.H., Basten, A.A., Tham, C.K., Geilen, M.C.W. & Corporaal, H. (2007). Analysing Qos Trade-offs in Wireless Sensor Networks. Proceedings of the 10 th ACM International Symposium on Modeling, Analysis and Simulation of Wireless and Mobile Systems (MSWIM 2007) 22-26 October 2007, Chania, Crete Island, Greece. (pp. 60-69). New York, New York: ACM Press.
Hu, H. & Haan, G. de (2007). Adaptive Image Restoration Based on Local Robust Blur Estimation. In J. Blanc-Talon & W. Philips (Eds.), Proceedings of the 9th international conference on Advanced Concepts for Intelligent Vision Systems (ACIVS 2007) 28-31 August 2007, Delft, The Netherlands. (Lecture Notes in Computer Science, Vol. 4678, pp. 461-472). Berlin, Germany: Springer.
Hu, H. & Haan, G. de (2007). Trained Bilateral Filters and Applications to Coding Artifacts Reduction. Proceedings of th 14th international Conference of Image Processing (ICIP 2007) 16-19 September 2007, San Antonio, Texas, USA. (pp. 325-328). Piscataway, New Jersey, USA: IEEE Computer Society.
Hu, H. & Haan, G. de (2007). Simultaneous Coding Artifact Reduction and Sharpness Enhancement. Digest of the ICCE. (pp. 213-214). Los Alamitos: IEEE Computer Society Press.
Huang, J. & Voeten, J.P.M. (2007). Predictable model-driven design for real-time embedded systems. Proc. of Bits & Chips conference 2007.
Huang, J., Voeten, J.P.M., Groothuis, M., Broenink, J. & Corporaal, H. (2007). A Model Driven Approach for Mechatronic Systems. Proceedings of the 7th International Conference on Application of Concurrency to System Design (ACSD 2007) 10-13 July 2007, Bratislava, Slovak Republic. (pp. 127-136). Piscataway NJ: IEEE.
Marescaux, T. & Corporaal, H. (2007). Introducing the superGT network-on-chip: SuperGT QoS: more than just GT. 44th ACM/IEEE Design Automation Conference, 2007 : DAC '07 ; 4 - 8 June 2007, [San Diego, CA] (pp. 116-121). Piscataway: IEEE Service Center.
Marescaux, T., Brockmeyer, E. & Corporaal, H. (2007). The impact of higher communication layers on NoC supported MP-SoCs. First International Symposium on Networks-on-Chip, 2007 : NOCS 2007 ; Princeton, New Jersey, 7 - 9 May 2007. (pp. 107-116). Los Alamitos: IEEE Computer Society.
Nollet, V., Verkest, D. & Corporaal, H. (2007). A Quick Safari Through the MPSoC Run-Time Management Jungle. Proceedings of the 5th Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2007), 4-5 October 2007, Salzburg, Austria. (pp. 41-46).
Palkovic, M., Corporaal, H. & Catthoor, F. (2007). Heuristics for scenario creation to enable general loop transformations. 2007 International Symposium on System-on-Chip, 20-21 November 2007, Tampere, Florida. (pp. 1-4). Piscataway.
Poplavko, P., Basten, A.A. & Meerbergen, J. van (2007). Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism. Proceedings of the 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) 29-31 August 2007, Lübeck, Germany. (pp. 228-235). Los Alamitos: IEEE Computer Society Press.
Pu, Y., Pineda de Gyvez, J., Corporaal, H. & Ha, Y. (2007). Vt balancing and device sizing towards high yield of sub-threshold static logic gates. Proc. of International Symposium on Low Power Electronics and Design. (pp. 355-358). Portland, USA.
Raghavan, P., Lambrechts, A., Jayapala, M., Catthoor, F., Verkest, D. & Corporaal, H. (2007). Very wide register: an asymmetric register file organization for low power embedded processors. Proc. of Design Automation and Test in Europe 2007. (pp. 1066-1071). Nice: IEEE Computer Society.
Shao, L., Hu, H. & Haan, G. de (2007). Coding Artifacts Robust Resolution Up-conversion. Proceedings of the 14th International Conference on Image Processing (ICIP 2007) 16-19 September 2007, San Antonio, Texas, USA. (pp. 409-412). San Antonio: IEEE Computer Society Press.
Sohler, W., Grundkötter, W., Herrmann, H., Hu, H., Jansen, S.L., Lee, J.H., Min, Y.H., Quiring, V., Ricken, R., Reza, S., Suche, H. & Wehrspohn, R.B. (2007). All-optical signal processing devices with (periodically poled) lithium niobate waveguides. Proceedings of the Conference on Optical Fiber Communication and the National Fiber Optic Engineers Conference, (OFC / NFOC 2007) 25-29 March 2007, Anaheim, California, USA. (pp. OME3-1/3). Piscataway, New Jersey, USA: IEEE Service Center.
Theelen, B.D. & Voeten, J.P.M. (2007). Performance modelling for system-level design. Tutorial Bits and Chips conf.: Performance modelling for system-level design.
Theelen, B.D. (2007). A performance Analysis Tool for Scenario-Aware Streaming Applications. Proceedings of the 4th International Conference on the Quantitative Evaluation of Systems (QEST 2007) 17-19 September 2007, Edinburgh, UK. (pp. 269-270). Los Alamitos: IEEE Computer Society.
Theelen, B.D., Geilen, M.C.W. & Voeten, J.P.M. (2007). Tutorial Memocode: Performance Modelling in Software/Hardware Engineering. Proceedings of the 5th ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2007), May 30 - June 1st, Nice, France. Nice.
Theelen, B.D., Florescu, O., Geilen, M.C.W., Huang, J., Putten, P.H.A. van der & Voeten, J.P.M. (2007). Sotware/Hardware Engineering with the Parallel Object-Oriented Specification Language. Proceedings of the 5th ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) 30 May - 2 June 2007, Nice, France. (pp. 139-148). IEEE Computer Society.
Theelen, B.D., Florescu, O., Geilen, M.C.W., Huang, J., Putten, P.H.A. van der & Voeten, J.P.M. (2007). Software/Hardware Engineering with the Parallel Object-Oriented Specification Language. Proceedings of the 5th ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) 30 May - 2 June 2007, Nice, France. (pp. 139-148). Piscataway, New Jersey, USA: IEEE Computer Society.
Zjajo, A., Barragan Asian, M.J. & Pineda de Gyvez, J. (2007). BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2007, DATE '07, 16-20 April 2007, Nice Acropolis, France. (pp. 1-6). New York: IEEE.

2006

Mesman, B., Fatemi, S.H., Corporaal, H. & Basten, A.A. (2006). Dynamic-SIMD for lens distortion compensation. Proceedings of Application-specific Systems, Architectures and Processors. (pp. 261-264). Los Alamitos USA: IEEE Computer Society Press.
Stuijk, S., Geilen, M.C.W. & Basten, A.A. (2006). Exploring Trade-offs in Buffer Requirements and Throughput Constraints for Synchronous Dataflow Graphs. Proceedings of the 43rd Design Automation Conference 2006. (pp. 899-904). New York, USA: ACM Press.
Stuijk, S., Geilen, M.C.W. & Basten, A.A. (2006). SDF3: SDF For Free. In K.G.W. Goossens & L. Petrucci (Eds.), Proceedings of the 6th International Conference ACSD 2006. (pp. 276-278). Los Alamitos, USA: IEEE Computer Society Press.
Stuijk, S., Basten, A.A., Geilen, M.C.W., Ghamarian, A.H. & Theelen, B.D. (2006). Resource-efficient Routing and Scheduling of Time-constrained Network-on-Chip Communication. In V. Muthukumar (Ed.), Proceedings of 9th EUROMICRO Conference, DSD 2006. (pp. 45-52). Los Alamitos, USA: IEEE Computer Society Press.
Bartels, C.L.L., Huisken, J., Goossens, K.G.W., Groeneveld, P.R. & Meerbergen, J. van (2006). Comparison of an æthereal network on chip and a traditional interconnect for a multi-processor DVB-T system on chip. 2006 IFIP International Conference on Very Large Scale Integration : Nice, France, 16 - 18 October 2006. (pp. 80-85). New York: IEEE.
Haan, G. de & Zhao, M. (2006). Invited paper: Making the best of legacy video on modern displays. Digest of the SID'06. (Vol. 37, pp. 1888-1891).
Groote, J.F., Mousavi, M.R. & Reniers, M.A. (2006). A hierarchy of SOS rule formats. In P.D. Mosses & I. Ulidowski (Eds.), Proceedings of the 2nd Workshop on Structural Operational Semantics (SOS2005, Lisbon, Portugal, July 10, 2005; satellite to ICALP2005). (Electronic Notes in Theoretical Computer Science, Vol. 156(1), pp. 3-25).
Mousavi, M.R. & Reniers, M.A. (2006). Prototyping SOS meta-theory in Maude. In P.D. Mosses & I. Ulidowski (Eds.), Proceedings of the 2nd Workshop on Structural Operational Semantics (SOS2005, Lisbon, Portugal, July 10, 2005; satellite to ICALP2005). (Electronic Notes in Theoretical Computer Science, Vol. 156(1), pp. 135-150).
Mousavi, M.R. (2006). Towards SOS meta-theory for language-based security. In L. Aceto & A.D. Gordon (Eds.), Proceedings of the Workshop "Essays on Algebraic Process Calculi" (APC 25, Bertinoro, Italy, August 1-5, 2005). (Electronic Notes in Theoretical Computer Science, Vol. 162, pp. 267-271).
Mousavi, M.R., Sirjani, M. & Arbab, F. (2006). Formal semantics and analysis of component connectors in Reo. Proceedings of the 4th International Workshop on the Foundations of Coordination Languages and Software Architectures (FOCLASA'05, San Francisco CA, USA, August 27, 2005; in conjunction with CONCUR'05). (Electronic Notes in Theoretical Computer Science, Vol. 154(1), pp. 83-99).
Fatemi, S.H., Mesman, B., Corporaal, H., Basten, A.A. & Jonker, P.P. (2006). Run-Time Reconfiguration of Communication in SIMD Architectures. Proceedings of the 20th International Parallel and Distributed Processing Symposium 20006, 13th Reconfigurable Architectures Workshop, RAW 2006. Los Alamitos, USA: IEEE Computer Society Press.
Kumar, Akash, Mesman, B., Corporaal, H., Meerbergen, J. van & Ha, Y. (2006). Global Analysis of Resource Arbitration for MPSoC. Proceedings of the 9th Euromicro Conference on Digital Systems Design. (pp. 71-78). Dubrovnik, Croatia: IEEE Computer Society.
Kumar, Akash, Mesman, B., Theelen, B.D., Corporaal, H. & Ha, Y. (2006). Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip. Proceedings of the IEEE Workshop on Embedded Systems for Real-Time Multimedia. (pp. 33-38). Los Alamitos, USA: IEEE Computer Society.
Kumar, Akash, Ovadia, I., Huisken, J., Corporaal, H., Meerbergen, J. van & Ha, Y. (2006). Reconfigurable Multi-Processor Network-on-Chip on FPGA. Proceedings of the 12th Annual Conference of the Advanced School for Computing and Imaging. (pp. 313-317).
Kumar, Akash, Theelen, B.D., Mesman, B. & Corporaal, H. (2006). On Composability of MPSoC Applications. Advanced Computer Architecture and Compilation for Embedded Systems. (pp. 149-152). Ghent, Belgium: Academia Press.
He, Y., Sint Annaland, M. van, Deen, N.G. & Kuipers, J.A.M. (2006). Gas-solid two-phase turbulent flow in a circulating fluidized bed riser: an experimental and numerical study. Proceedings of the 5th World Congress on Particle Technology (WCPT5), 23 April 2006, Orlando, Florida, USA.
Aa, T. van der, Jayapala, M., Corporaal, H. & Deconinck, G. (2006). Efficient Architecture Exploration of a Clustered Loop. Proceedings of the Internation Workshop on Optimizations for DSPS and Embedded Ssytems.
Aa, T. van der, Jayapala, M., Catthoor, F., Deconinck, G. & Corporaal, H. (2006). Instruction Transfer and Storage Exploration for Low Energy VLIWS. Proceedings of IEEE 2006 Workshop on Signal Processing Systems. (pp. 313-318). Los Alamitos: IEEE Computer Society.
Beric, A., Sethuraman, R., Alba Pinto, C.A., Peters, H., Veldman, G., Haar, P. van de & Duranton, M. (2006). Heterogeneous multiprocessor for high definition video. Proceedings of the IEEE International Conference on Consumer Electronics. (pp. 401-402).
Caarls, W., Jonker, P.P. & Corporaal, H. (2006). Algorithmic Skeletons for Stream Programming en Embedded Heterogeneous Parallel Image Processing Applications. Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium. Los Alamitos: IEEE Computer Society.
Ciordas, C., Goossens, K.G.W., Basten, A.A., Radulescu, A. & Boon, A.G. (2006). Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective. Proceedings of IEEE Symposium on Industrial Embedded Systems. Los Alamitos: IEEE Computer Society Press.
Ciordas, C., Goossens, K.G.W., Radulescu, A. & Basten, A.A. (2006). NoC Monitoring: Impact on the Design Flow. Proceedings the IEEE International Symposium on Circuits and SYStems, 2006. (pp. 1981-1984). Los Alamitos, USA: IEEE Computer Society Press.
Ciordas, C., Hansson, M.A., Goossens, K.G.W. & Basten, A.A. (2006). A Monitoring-aware NoC Design Flow. In V. Muthukumar (Ed.), Proceedings of the 9th EUROMICRO Conference, DSD 2006. (pp. 97-104). Los Alamitos, USA: IEEE Computer Society Press.
Florescu, O., Voeten, J.P.M., Verhoef, M. & Corporaal, H. (2006). Reusing Real-Time Systems Design Eperience Through Modelling Patterns. Proceedings of the Forum on Specification & Design Languages 2006. (pp. 375-380).
Florescu, O., Hoon, M.M.C.M. de, Voeten, J.P.M. & Corporaal, H. (2006). Performance Modelling and Analysis Using POOSL for an In-Car Navigation System. Proceedings of the 12th Annual Conference of the Advanced School for Computing and Imaging . (pp. 37-45).
Florescu, O., Hoon, M.M.C.M. de, Voeten, J.P.M. & Corporaal, H. (2006). Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems. Proceedings of the Embedded Computer Systems: architectures, Modeling and Simulation. (pp. 206-215).
Florescu, O., Huang, J., Voeten, J.P.M. & Corporaal, H. (2006). Strengthening Property Preservation in Concurrent Real-Time Systems. Proceedings of the IEEE International Conference on Embedded and Real-Time Computing Systems and Applications. (pp. 106-109). Los Alamitos, USA: IEEE Computer Society.
Ghamarian, A.H., Geilen, M.C.W., Stuijk, S., Basten, A.A., Moonen, A.J.M., Bekooij, M.J.G., Theelen, B.D. & Mousavi, M.R. (2006). Throughput analysis of synchronous data flow graphs. In K.G.W. Goossens & L. Petrucci (Eds.), Proceedings 6th International Conference on Application of Concurrency to System Design (ACSD 2006,Turku, Finland, June 28-30, 2006). (pp. 25-36). Brussels: IEEE Computer Society Press.
Ghamarian, A.H., Geilen, M.C.W., Basten, A.A., Theelen, B.D., Mousavi, M.R. & Stuijk, S. (2006). Liveness and Boundedness of Synchronous Data Flow Graphs. Proceedings of the 6th International Conference on Formal Methods in Computer-Aided Design. (pp. 68-75). Los Alamitos, USA: IEEE Computer Society.
Gheorghita, Valentin, Basten, A.A. & Corporaal, H. (2006). Application Scenarios in Streaming-Oriented Embedded Systems Design. Proceedings of the International Symposium on System-on-Chip 2006. (pp. 175-178). Piscataway, USA: IEEE.
Gheorghita, Valentin, Basten, A.A. & Corporaal, H. (2006). Handling Dynamism in Embedded system Design by Application Scenarios. Proceedings of Architecture and Compilers for Embedded Systems Symposium 2006. (pp. 5-8).
Gheorghita, Valentin, Basten, A.A. & Corporaal, H. (2006). Profiling Driven Scenario Detection and Prediction for Multimedia Applications. Proceedings of Embedded Computer Systems: architectures, modelling and simulation, International Conference, IC-SAMOS. (pp. 63-70). Los Alamitos, USA: IEEE Computer Society Press.
Goel, S.K., Meijer, M. & Pineda de Gyvez, J. (2006). Test and Diagnosis of Power Switches in SOCs. Proceedings of the IEEE European Test Symposium. (pp. 145-151).
Heesch, F.H. van, Klompenhouwer, M.A. & Haan, G. de (2006). Masking coding artifacts on large displays. Proceedings of the International Conference on Consumer Elecronis, 2006. (pp. 207-208).
Hu, H. & Haan, G. de (2006). Classification-based hybrid filters for image processing. Proceedings of SPIE, Visual Communications and Image Processing. onbekend.
Hu, H. & Haan, G. de (2006). Low cost robust blur estimator. Proceedings of IEEE International Conference On Image Processing ICIP 2006. (pp. 617-620). Los Alamitos, USA: IEEE Society Press.
Huang, J., Voeten, J.P.M. & Corporaal, H. (2006). Correctness-preserving Synthesis for Real-Time Control Software. In Mei Hong (Ed.), Proceedins of the International Conference on Quality Software. (pp. 65-73). Los Alamitos, USA: IEEE Computer Society.
Huang, J., Geilen, M.C.W., Voeten, J.P.M. & Corporaal, H. (2006). Branching-time property preservation between real-time systems. In Susanne Graf & Wenhui Zhang (Eds.), Proceedings of the International Symposium on Automated Technology for Verification and Analysis. (pp. 260-275). Berlin, Germany: Springer-Verlag.
Nollet, V., Avasare, P., Verkest, D. & Corporaal, H. (2006). Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment. Proceedings of the Internation Conference on Engineering of Systems and Algorithms. (pp. 49-55).
Palkovic, M., Catthoor, F. & Corporaal, H. (2006). Automatic Model Generation for Evaluation of Scenario Creation Heuristics. Proceedings of the 6th Symposium on Architecture and Compilers for Embedded Systems. (pp. 1-4).
Palkovic, M., Catthoor, F. & Corporaal, H. (2006). Dealing with variable trip count loops in system level exploration. Proceedings of the 4th Workshop on Optimizations for DSP and Embedded Systems. (pp. 19-28).
Pastrnak, M., With, P.H.N. de & Meerbergen, J. van (2006). Realization of QoS Management Using Negotiation algorithms for Multiprocessor NoC. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006) 21 - 24 May 2006, Island of Kos, Greece. (pp. 1912-1915). Piscataway, New Jersey, USA: IEEE.
Pastrnak, M., With, P.H.N. de, Stuijk, S. & Meerbergen, J. van (2006). Parallel Implementation of Arbitrary-Shaped MPEG-4 Decoder for Multiprocessor Systems. In John G. Apostolopoulos & Amir Said (Eds.), Proceedings of Visual Communications and Image Processing. (pp. 60771-1-60771-10). Bellingham, USA: IS&T Society for Imaging Science and Technology.
Pastrnak, M., With, P.H.N. de, Ciordas, C., Meerbergen, J. van & Goossens, K.G.W. (2006). Mixed adaptation and fixed-reservation QoS for improving picture quality and resource usage of multimedia (NoC) chips. 2006 IEEE 10th International Symposium on Consumer Electronics, ISCE 2006, 28 June 2006 through 1 July 2006, St.Petersburg. (pp. 207-212). Piscataway: IEEE.
Pu, Y., Sing, L.C., Ha, Y. & Corporaal, H. (2006). Power-efficient FPGA switch with reconfigurable buffers. proceedings of the Internation PhD Student Workshop on SoC. Taipei, Taiwan.
Spaanenburg, L., Akesson, K.B., Hansson, M.A. & Goossens, K.G.W. (2006). Design method for unconventional computing. Proc. 2006 10th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA 2006, 28 August 2006 through 30 August 2006, Istanbul. (pp. 1-6). Picataway: IEEE.
Theelen, B.D., Geilen, M.C.W., Basten, A.A., Voeten, J.P.M., Gheorghita, Valentin & Stuijk, S. (2006). A Scenario-Aware Data Flow Model for Combined Long-Run Average and Worst-Case Performance Analysis. Proceedings of the ACM-IEEE International Conference on Formal Methods and Models for Codesign. (pp. 185-194). Los Alamitos, USA: IEEE Computer Society.
Visser, M., Muiswinkel, A. van, Ciuhu, C. & Haan, G. de (2006). Enhanced MRI resolution for clinical applications. Proceedings of the ISMRM 14th Scientific meeting & exhibition.
Ykman-Couvreur, Ch., Nollet, V., Catthoor, F. & Corporaal, H. (2006). Fast Multi-Dimentsion Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management. Proceedings of the International Symposium on System-on-Chip. (pp. 195-198).
Ykman-Couvreur, Ch., Nollet, V., Marescaux, T., Brockmeyer, E., Catthoor, F. & Corporaal, H. (2006). Pareto-Based Application Specification for MPSoC Customized Run-Time Management. Proceedings of the International Conference on Embedded Computer Systems: Architecturs, Modeling and Simulation. (pp. 78-84).

2005

Voeten, J.P.M., Huang, J., Florescu, O., Theelen, B.D. & Corporaal, H. (2005). Towards predictability in real-time embedded system design. Invited presentation. Proceedings of the Lorentz-ARTIST (Network of Excellence on Embedded Systems Design) Workshop Embedded Systems.
Voeten, J.P.M., Putten, P.H.A. van der, Theelen, B.D. & Florescu, O. (2005). Performance modelling for stem-level Design. Tutoral at the Euromicro conference on Digital System Design 2005.
Geilen, M.C.W., Basten, A.A. & Stuijk, S. (2005). Minimising Buffer Requirements of Synchronous Dataflow Graphs with Model Checking. Proceedings of the 42nd Design Automation Confernce, DAC 2005. (pp. 819-824). New York: ACM Press.
Geilen, M.C.W., Basten, A.A., Theelen, B.D. & Otten, R.H.J.M. (2005). An Algebra of Pareto Points. In J. Desel & Y. Watanabe (Eds.), Proceedings of the 5th Application of Concurrency to System Design 2005 conference. (pp. 88-97). Los Alamitos: IEEE Computer Society Press.
Stuijk, S., Basten, A.A., Mesman, B. & Geilen, M.C.W. (2005). Predictable embedding of large data structures in multiprocessor networks-on-chip. In C. Wolinski (Ed.), Proceedings of he 8th EUROMICRO Conference on Digital System Design. (pp. 388-395). Los Alamitos: IEEE Compuer Society Press.
Stuijk, S., Basten, A.A., Mesman, B. & Geilen, M.C.W. (2005). Predictable embedding of large data stuctures in multiprocessor networks-on-chip (extended abstract). In N. Wehn & L Benini (Eds.), Proceedings of DATE 05. (pp. 254-255). Los Alamitos: IEEE Computer Society Press.
Fatemi, S.H., Corporaal, H., Basten, A.A., Kleihorst, R.P. & Jonker, P.P. (2005). Designing area and performance constrained SIMD/VLIW image processing architectures. In J. Blanc-Talon, W. Philips, D. Popescu & P. Scheunders (Eds.), Advanced concepts for intelligent vision systems : 7th international conference, ACIVS 2005, Antwerp, Belgium, September 20-23, 2005 : proceedings. (Lecture Notes in Computer Science, Vol. 3708, pp. 689-696). Berlin: Springer.
Fatemi, S.H., Corporaal, H., Basten, A.A., Kleihorst, R.P. & Jonker, P.P. (2005). Parallelism Support in SIMD/VLIW Image Processing Architectures. In B.J.A. Krose, H.J. Bos, E.A. Hendriks & J.W.J. Heijnsdijk (Eds.), Proceedings of the 11th Annual Conference of the Advanced School for Computing and Imaging. (pp. 291-296). Delft: ASCI.
Aa, T. van der, Corporaal, H., Catthoor, F. & Deconinck, G. (2005). Combining data and instruction memory energy optimizations for embedded applications. In M. Miranda & S. Ha (Eds.), Proceedings of the 3rd workshop on Embedded Systems for Real-Time Multimedia 2005. (pp. 121-126). IEEE.
Aa, T. van der, Jayapala, M., Barat, F., Corporaal, H., Catthoor, F. & Deconinck, G. (2005). A High Level Memory Energy Estimator based on Reuse Distance. Proceedings of 3rd workshop on Optimizations for DSP and Embedded Systems, ODES 2005 together with CGO 2005.
Avasare, P., Nollet, V., Mignolet, J.-Y., Verkest, D. & Corporaal, H. (2005). Centralized End-to-End Flow Control in a Best-Effort Network-on-Chip. Proceedings of the EMSOFT conference 2005. (pp. 17-20).
Barat, F., Aa, T. van der, Jayapala, M., Deconinck, G., Lauwereins, R. & Corporaal, H. (2005). Methodology for building processor design space exploration frameworks. Proceedings of 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES 2005).
Bekooij, M.J.G., Parmar, S. & Meerbergen, J. van (2005). Performance Guarantees by Simulation of Process Networks. Proceedings of the Scopes Workshop 2005. Springer.
Beric, A., Haan, G. de, Sethuraman, R. & Meerbergen, J. van (2005). Algorithm/Architecture Co-design of the Generalized Sampling Theorem Based De-Interlacer. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2005) 23 - 26 May 2005, Kobe, Japan. (pp. 2943-2946). Piscataway, New Jersey, USA: IEEE.
Beric, A., Sethuraman, R., Meerbergen, J. van & Haan, G. de (2005). Memory-Centric Motion Estimator. Proceedings IEEE Conference on VLSI Design, January 2005. (pp. 816-819).
Caarls, W., Jonker, P.P. & Corporaal, H. (2005). Skeletons and Asynchronous RPC for Embedded Data- and task Parallel Image Processing. In K Ikeuchi (Ed.), Proceedings of the 9th IAPR Conference on Machine Vision Applications 2005.
Ciuhu, C. & Haan, G. de (2005). Motion Estimation on Interlaced Video. Proceedings of SPIE, Image and Video COmmunications and Processing, January 2005.
Florescu, O., Voeten, J.P.M. & Corporaal, H. (2005). Property-Preservation Synthesis for Unified Control- and Data-Oriented Models. Proceedings of the Forum on Specification & Design Languages (FDL) 2005. (pp. 531-542). Lausanne: FDL.
Gheorghita, Valentin & Grigore, R. (2005). Constructing Checkers from PSL Properties. Proceedings of the 15h Int. Conference on Control Systems and Computer Science. (Vol. 2, pp. 757-763).
Gheorghita, Valentin, Stuijk, S., Basten, A.A. & Corporaal, H. (2005). Automatic Scenario Detection for Improved WCET Estimation. Proceedings of the 42nd Design Automation Conference, DAC 2005. (pp. 101-104). New York: ACM Press.
Gheorghita, Valentin, Basten, A.A. & Corporaal, H. (2005). Intra-task Scenario-aware Volgage Scheduling. Proceedings of CASES'2005. (pp. 177-184). New York: ACM Press.
Hansson, M.A., Goossens, K.G.W. & Radulescu, A. (2005). A unified approach to constrained mapping and routing on network-on-chip architectures. CODES+ISSS 2005 : International Conference on Hardware/Software Codesign and System Synthesis ; September 18 - 21, 2005, Jersey City, New Jersey, USA. (pp. 75-80). New York: Association for Computing Machinery.
Hansson, M.A., Goossens, K.G.W. & Radulescu, A. (2005). A unified approach to constrained mapping and routing on network-on-chip architectures. Proc. of Int. Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). (pp. 75-80). ACM.
Heesch, F.H. van, Klompenhouwer, M.A. & Haan, G. de (2005). Masking Noise in Up-scaled Video on Large Displays. IEEE Digest of the ICCE'05, Session 11.3, paper 4.
Heikkinen, J., Cilio, A.G.M., Takala, J. & Corporaal, H. (2005). Dictionary-Based Program Compression on transport Triggered Architectures. Proceedings IEEE Int. Symposium on Circuits and Systems. (pp. 1122-1125).
Heikkinen, J., Takala, J. & Corporaal, H. (2005). Dictionary-Based Program Compression on TTAs: Effects on Area and Power Consumption. Proceedings of IEEE Workshop on Signal Processing Systems. (pp. 479-484).
Hu, H., Hofman, M. & Haan, G. de (2005). Content-adaptive neural filters for image interpolation using pixel classification. Proceedings of SPIE, Applications of Neural Networks and Machine Learning in Image Processing IX, January 2005.
Huang, J., Voeten, J.P.M., Florescu, O., Putten, P.H.A. van der & Corporaal, H. (2005). Predictability in Real-Time System Development. In P. Boulet (Ed.), Advances in Design and Specification Languages for SoCs, Chapter 8. Dordrecht, the Netherlands: Kluwer Academic Publishers.
Jaghoori, M.M., Sirjani, M., Mousavi, M.R. & Movaghar, A. (2005). Efficient symmetry reduction for an actor-based model. In G. Chakraborty (Ed.), Distributed Computing and Internet Technology (Proceedings Second International Conference, ICDCIT 2005, Bhubaneswar, India, December 22-24, 2005). (Lecture Notes in Computer Science, Vol. 3816, pp. 494-507). Berlin: Springer-Verlag.
Lambrechts, A., Raghavan, P., Leroy, A., Talavera, G., Aa, T. van der, Jayapala, M., Catthoor, F., Verkest, D., Deconinck, G., Corporaal, H., Robert, F. & Carrabina, J. (2005). Power breakdown analysis for a Heterogeneous NoC Platform running a video Application. Proceedings of IEEE 16th International Conference on Application-specific Systems, Architectures and Processors ASAP 2005.
Lu, R.X., Silva, C., Ang, M.H., Poo, J.A.N. & Corporaal, H. (2005). A New Approach for Mechatonic System Design: Mechatronic Design Quotient (MDQ). Proceedings of the 2000 IEEE/ASME nternational Conferen on Advanced Intelligent Mechatronics. (pp. 911-915).
Marescaux, T., Bricke, B., Debacker, P., Nollet, V. & Corporaal, H. (2005). Dynamic Time-Slot Allocation for QoS Enabled Networks on Chip. Proceedings of the 3rd Workshop on Embedded Systems for Real-Time Multimedia 2005. (pp. 47-52). IEEE.
Marescaux, T., Rangevall, A., Nollet, V., Bartic, A. & Corporaal, H. (2005). Distributed congestion control for packet switched networks on chip. Proceedings of Parallel Computing Conference PARCO'05.
Meijer, M., Pineda de Gyvez, J. & Otten, R.H.J.M. (2005). On-chip digital power supply control for system-on-chip applications. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, ISLPED '05, 8-10 August 2005. (pp. 311-314). Piscataway: IEEE Service Center.
Moonen, A.J.M., Berg, R.M.J. van den, Bekooij, M.J.G., Bhullar, H. & Meerbergen, J. van (2005). A Multi-Core Architecture for In-Car Digital Entertainment. Proceedings of GSPx Conference.
Moreira, O., Mol, J.J.D., Bekooij, M.J.G. & Meerbergen, J. van (2005). Multiprocessor Resource Allocation for Hard-real-time Streaming with a Dynamic job-mix. Proceedings of IEEE Real-time and Embedded Technology and Applications Symposium, San Francisco, March 2005.
Ovadia, I., Ha, Y. & Corporaal, H. (2005). Using Multiple Paths in NoCs for Guaranteed Resource Allocation and Improved Best Effort Performance in NoCs. Proceedings of the 16th ProRISC, Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2005) 17 - 18 November 2006, Veldhoven, the Netherlands. (pp. 564-569). Utrecht, the Netherlands: Technology Foundation.
Palkovic, M., Corporaal, H. & Catthoor, F. (2005). Global memory optimisation for embedded systems allowed by code duplication. Proceedings of International Workshop on Software and Compilers for Embedded Systems, SCOPES 2005. (pp. 72-79).
Palkovic, M., Corporaal, H. & Catthoor, F. (2005). Scenario creation for low power embedded systems. Proceedings of Architectures and Compilers for Embedded Systems ACES 2005. (pp. 26-29).
Palkovic, M., Brockmeyer, E., Vanbroekhoven, P., Corporaal, H. & Catthoor, F. (2005). Systematic preporocessing of data dependent constructs for embedded systems. Proceedings of 15th international workshop Integrated Circuit and System Design. Power and Timing Modeling Optimization and Simulation, PATMOS 2005. (pp. 88-99).
Pastrnak, M., Poplavko, P., With, P.H.N. de & Meerbergen, J. van (2005). Hierarchical QoS concept for multiprocessor system-on-chip. Proc. IEEE Benelux CE Workshop on resource management for media processing in networked embedded systems. (pp. 139-142).
Pastrnak, M., Poplavko, P., With, P.H.N. de & Meerbergen, J. van (2005). Novel QoS model for mapping of MPEG-4 coding onto MP-NoC. Proc. 9th IEEE International symposium on Consumer electronics (ISCE). (pp. 93-98).
Poplavko, P., Basten, A.A., Pastrnak, M., Meerbergen, J. van, Bekooij, M.J.G. & With, P.H.N. de (2005). Estimation times of on-chip multiprocessor stream-oriented applications. Proceedings of the Third ACM-IEEE Internat. conf. on formal Methods and Models for Co-Design (MEMOCODE 2005). (pp. 250-251). Verona, Italy.
Poplavko, P., Basten, A.A., Pastrnak, M., Meerbergen, J. van, Bekooij, M.J.G. & With, P.H.N. de (2005). Extended Abstract: Estimation of Execution Times of On-chip Multiprocessors Stream-oriented Applications. Formal Methods and Models for Codesign, 3rd ACM & IEEE Int. Conference, MEMOCODE 2005, proceedings. (pp. 251-252). Los Alamitos: IEEE Computer Society Press.
Sénéclauze, M., Decotignie, J.D., Stok, P.D.V. van der, Groot, H. de, Hartskamp, M.A. van, Doren, G. van, Heesch, D., Otero Perez, C., Joosten, M., Blanch, C., Bormans, J., Geilen, M.C.W., Basten, A.A., Theelen, B.D., Koulamas, C., Papadopoulos, G., Prayati, A., Fohler, G., Isovic, D., Papadopoulos, G.A., Cheng, P. & Abraham, Z. (2005). The BETSY project on timeliness and energy aspects of wireless video streaming. International Workshop on Wireless Ad-hoc Networks (IWWAN'05, London, UK, May 23-26, 2005), Online proceedings. (pp. 25). Abstract.
Terechko, A., Garg, M. & Corporaal, H. (2005). Evaluation of Speed and Area of Clustered VLIW Processors. Proceedings of the 18th Int. Conference on VLSI Design and the 4th Int. Conference on Embedded Systems Design. (pp. 557-563). IEEE Computer Society.
Theelen, B.D., Voeten, J.P.M., Putten, P.H.A. van der & Florescu, O. (2005). System-Level Performance Analysis. Tutorial. Proceedings of the Euromicro Conference on Digital System Design 2005.
Ykman-Couvreur, Ch., Brockmeyer, E., Nollet, V., Marescaux, T., Catthoor, F. & Corporaal, H. (2005). Design-Time Application Exploration for MP-SoC Customized Run-Time Management. Proceedings of System-on-Chip Conference (SoC '05). (pp. 66-69).
Zhao, M. & Haan, G. de (2005). Content adaptive vertical temporal filtering for de-interlacing. Proceedings of the 9th INternational Symposium on Consumer Electronics, 2005 ISCE 2005 (pdf-file 493 kB). (pp. 69-73).
Zhao, M. & Haan, G. de (2005). Subjective evaluation of de-interlacing techniques. Proceedings of SPIE, Image and Video Communications and Processing, January 2005.
Zhao, M., Ciuhu, C. & Haan, G. de (2005). Classification based data mixing for hybrid de-interlacing techniques. Proceedings of the 13th European Signal Processing Conference, EUSIPCO 2005. (pdf-file, 348 kB).
Zjajo, A. & Pineda de Gyvez, J. (2005). Evaluation of signature-based testing of RF/analog circuits. Proceedings of the 10th IEEE European Test Symposium, 2005, 22-25 May 2005, Tallinn, Estonia. (pp. 62-67). Piscataway: IEEE Service Center.
Zjajo, A., Pineda de Gyvez, J. & Gronthoud, G. (2005). A quasi-static approach for detection and simulation of parametric faults in analog and mixed-signal circuits. Proceedings of the IEEE Int. Mixed Signal Test Workshop, June 2005.
Zjajo, A., Bergveld, H.J., Schuttert, R.F. & Pineda de Gyvez, J. (2005). Power-scan chain : design for analog testability. Proceedings of the IEEE International Test Conference, ITC 2005, 8 November 2005, Austin, Texas. (pp. 4.3-1/8). Piscataway: IEEE Service Center.

2004

Geilen, M.C.W. & Basten, A.A. (2004). Reactive Process Networks. Proc. of EMSOFT 2004, Forth ACM Int. Conference on Embedded Software. (pp. 137-146). Pisa, Italy: ACM Press, N.Y., USA.
Mousavi, M.R., Reniers, M.A., Basten, A.A. & Chaudron, M.R.V. (2004). PARS: A Process Algebra with Resources and Schedulers. In K.G. Larsen & P. Niebert (Eds.), Formal Modeling and Analysis of Timed Systems (First International Workshop, FORMATS 2003, Marseille, France, September 6-7, 2003, Revised Papers). (Lecture Notes in Computer Science, Vol. 2791, pp. 134-150). Berlin: Springer-Verlag.
Mousavi, M.R., Le Guernic, P., Talpin, J.-P., Shukla, S.K. & Basten, A.A. (2004). Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks. Proceedings 7th Design, Automation and Test in Europe Conference and Exposition (DATE 04, Paris, France, February 18-20, 2004), volume 1. (pp. 384-389). Los Alamitos CA: IEEE Computer Society Press.
Fatemi, S.H., Corporaal, H., Basten, A.A., Jonker, P.P. & Kleihorst, R.P. (2004). Implementing face recognition using a parallel image processing environment based on algorithmic skeletons. In J.J. van Wijk, J.W.J. Heijnsdijk, K.G. Langedoen & R. Veltkamp (Eds.), Proceedings of the 10th Annual Conference of the Advanced School for COmputing and Imaging. (pp. 351-357). Port Zelande, the Netherlands: ASCI, Delft, the Netherlands.
Aa, T. van der, Jayapala, M., Barat, F. & Corporaal, H. (2004). Instruction and Data Memory Energy Trade-off using a High-level Model. Proc. of 2nd Workshop on Optimizations for DSP and Embedded Systems. Palo Alto, CA, USA.
Aa, T. van der, Jayapala, M., Barat, F., Deconinck, G., Lauwereins, R., Catthoor, F. & Corporaal, H. (2004). Instruction Buffering Exploration for Low Energy VLIWs with Instruction Clusters. Proc. of the Asian Pacific Design and Automation Conference 2004, Yokohama, Japan. (pp. 824-829).
Barat, F., Jayapala, M., Aa, T. van der, Deconinck, G., Lauwereins, R. & Corporaal, H. (2004). Procesador VLIW reconfigurable para aplicaciones multimedia. FPGAs Computation y aplicaciones, (IV jornadas de computacion reconfigurable y aplicaciones).
Bekooij, M.J.G., Moreira, O., Poplavko, P., Meman, B., Pastrnak, M. & Meerbergen, J. van (2004). Predictable embedded multiprocessor system design. Proc. of 8th International Workshop on Software and Compilers for Embedded Systems (SCOPES)sofee. (pp. 77-91). Springer Verlag.
Beric, A., Sethuraman, R., Meerbergen, J. van & Haan, G. de (2004). A 27 mW 1.1 sq mm motion estimator for picture-rate up-converter. Proceedings of 17th International Conference on VLSI Design 2004.
Beric, A., Sethuraman, R., Peters, H., Veldman, G., Meerbergen, J. van & Haan, G. de (2004). Streaming scratchpad memory organisation for video applications. Proceedings of the IAESTED Int. Conference on Ciruits Signals and Systems 2004. (pp. 427-432).
Braspenning, R.A. & Haan, G. de (2004). True-motion estimation using feature correspondence. Proceedings of SPIE VCIP 2004. (pp. 396-407).
Caarls, W., Jonker, P.P. & Corporaal, H. (2004). Data- and task parallel image processing on a mixed SIMD-ILP platform using skeletons and asynchronous RPC. In M. Schweizer (Ed.), Proceedings 5th PROGRESS Symposium on Embedded Systems (Nieuwegein, The Netherlands, October 20, 2004). (pp. 1-8). Utrecht: STW.
Ciordas, C., Basten, A.A., Radulescu, A., Goossens, K.G.W. & Meerbergen, J. van (2004). An Event-Based Network-on-Chip Monitoring Service. Proceedings of 9th Annual IEEE Int. High Level Design Validation and Test Workshop 2004. (pp. 149-154). Sonoma Valley, CA, USA: IEEE Computer Society Press.
Ciuhu, C. & Haan, G. de (2004). A two-dimensional generalized sampling theory and application to de-interlacing. Proceedings of SPIE VCIP 2004. (pp. 700-711).
Cordes, C.N. & Haan, G. de (2004). Y/C-separation of composite color video signals using samples with non-opposite subcarrier phase. Proceedings of SPIE, VCIP 2004. (pp. 741-752).
Florescu, O., Voeten, J.P.M. & Corporaal, H. (2004). A Unified Model for Analysis of Real-Time Properties. Preliminary proc. of the 1st Int. Symposium on Leveraging Applications of Formal Methods. (pp. 220-227). Paphos, Cyprus.
Florescu, O., Voeten, J.P.M., Huang, J. & Corporaal, H. (2004). Error Estimation in Model-Driven Development for Real-Time Software. Proceedings of the Forum on specification and Design Langeuages. (pp. 228-239). Lille, France: ESCI, Gieres, France.
Garcea, G.S., Meijs, N.P. van der & Otten, R.H.J.M. (2004). Statistically aware buffer planning. Proceedings of DATE 2004, March 3-7. (pp. 1401-1403). Munich, Germany.
Gheorghita, Valentin, Corporaal, H. & Basten, A.A. (2004). Using Iterative Compilation to Reduce Energy Consumption. In J.J. van Wijk, J.W.J. Heijnsdijk, K.G. Langedoen & R. Veltkamp (Eds.), Proceedings of the 10th Annual Conference of the Advanced School for Computing and Imaging. (pp. 197-202). Port Zelande, the Netherlands: ASCI, Delft, the Netherlands.
Hu, H., Hofman, P.M. & Haan, G. de (2004). Image Interpolation Using Classification-based Neural Networks. Proc. of the ISCE. (pp. 133-137). Reading (UK: IEEE.
Huang, J. & Voeten, J.P.M. (2004). Predictability in real-time systems development : a case study. Proceedings of the Forum on Specification and Design Languages 2004. Gieres, France: ESCI.
Huang, J. & Voeten, J.P.M. (2004). Predictability in real-time systems development : semantics support for development languages. Proceedings of the Forum on Specification and Design Languages 2004. Lille, France: ESCI, Gieres, France.
Huang, J., Voeten, J.P.M. & Geilen, M.C.W. (2004). Real-time property preservation in concurrent real-time systems. Proceedings of the 10th Int. conference on Real-time and Embedded Computing Systems and Applications. Gothenburg, Sweden: Springer Verlag.
Jayapala, M., Aa, T. van der, Barat, F., Corporaal, H., Catthoor, F. & Deconinck, G. (2004). L0 Buffer Energy Optimization Through Scheduling and Exploration. Proc. of ACM Symposium on Applied Computing (SAC) 2004. (pp. 905-906).
Jayapala, M., Aa, T. van der, Barat, F., Catthoor, F., Corporaal, H. & Deconinck, G. (2004). L0 Cluster Synthesis and Operation Shuffling. Proc. of 14th Int. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS. (pp. 311-321).
Klompenhouwer, M.A. & Haan, G. de (2004). Video, Display and Processing. Digest of the SID'04. (pp. 1466-1469).
Lambrechts, A., Aa, T. van der, Jayapala, M., Leroy, A., Talavera, G., Shickova, A., Barat, F., Mei, B., Catthoor, F., Verkest, D., Deconinck, G., Corporaal, H., Robert, F. & Carrabina, J. (2004). Design style case study for embedded multi media compute nodes. Proc. of IEEE Int. Real-Time Systems Symposium 2004.
Moonen, A.J.M., Bekooij, M.J.G. & Meerbergen, J. van (2004). Timing analysis model for network based multiprocessor systems. Proceedings of the 15th ProRISC, Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2004) 25 - 26 November 2004, Veldhoven, the Netherlands. (pp. 91-99). Utrecht, the Netherlands: STW, Technology Foundation.
Palkovic, M., Brockmeyer, E., Corporaal, H., Catthoor, F. & Vounckx, J. (2004). Hierarchical rewriting and hiding of data dependent conditions to enable global loop transformations. 2nd ODES: Workshop on Optimizations for DSP and Emedded Systems, Palo Alto, USA.
Palkovic, M., Brockmeyer, E., Vanbroekhoven, P., Corporaal, H. & Catthoor, F. (2004). Augmenting the Exploration Space for Global Loop Transformations by Systematic Preprocessing of Data Dependent Constructs. Proc. of 4th Program accelaration by Application-driven & architecture-drive Code Transformations Symposium. Edegem, Belgie.
Pastrnak, M., Poplavko, P., With, P.H.N. de & Farin, D.S. (2004). Data-flow Timing Models of Dynamic Multimedia Applications for Multiprocessor Systems. Proc. 4th IEEE Int. Workshop on System-on-Chip for Real-Time Applications (SoCRT). (pp. 206-209). Los Alamitos, CA, USA: IEEE Computer Society Press.
Westra, H.J.L., Bartels, C.L.L. & Groeneveld, P.R. (2004). Probabilistic congestion prediction. Proceedings of the Int. Symposium on Physical Design. (pp. 204-209). Hyatt Regency, Phoenix Arizona, USA.
Zhao, M. & Haan, G. de (2004). Intra-field De-interlacing with Advanced Up-scaling Methods. Proc. of the ISCE. (pp. 315-319). Reading U.K.: IEEE.
Zhao, M., Hofman, P.M. & Haan, G. de (2004). Content-adaptive up-scaling of chrominance using classification of luminance and chrominance data. Proceedings of Electronic Imaging 2004. (pp. 299-304). Reading U.K.
Zhao, M., Hofman, P.M. & Haan, G. de (2004). Content-adaptive up-scaling of chrominance using classification of luminance and chrominance data. Proceedings of SPIE VCIP 2004. (pp. 721-730).
Zhao, M., Kneepkens, R.E.J., Hofman, P.M. & Haan, G. de (2004). Content Adaptive Image De-blocking. Proc. of the ISCE. (pp. 299-304).

2003

Otten, R.H.J.M. (2003). Wire Planning for Timing Closure. Invited talk. Proceedings of SASIMI 2003, April 304, Hiroshima, Japan. (pp. 303-310).
Jess, J.A.G., Kalafala, K., Naidu, S.R., Otten, R.H.J.M. & Visweswariah, C. (2003). Statistical timing for parametric yield prediction of digital integrated circuits. Proceedings of the 40th ACM/IEEE Design Automation Conference. (pp. 932-937).
Verbeek, H.M.W. & Basten, A.A. (2003). Deciding life-cycle inheritance on Petri nets. In W.M.P. van der Aalst & E. Best (Eds.), Applications and Theory of Petri Nets 2003, 24th international conference ICATPN 2003, proceedings. Lecture notes in Computer Science 2679. (pp. 44-63). Berlin, Germany: Springer.
Geilen, M.C.W. & Basten, A.A. (2003). Requirements on the Execution of Kahn Process Networks. Programming Languages and Systems, 12th European Symposium on Programming, ESOP 2003, held as part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2003. (Vol. 2618, pp. 319-334). Berlin, Germany: Springer Verlag.
Geilen, M.C.W. (2003). An improved on-the-fly tableau construction for a real-time temporal logic. Proc. of Computer Aided Verification 2003. (Vol. 2725). Berlin, Germany: Springer Verlag.
Stuijk, S. & Basten, A.A. (2003). Analyzing Concurrency in Computational Networks. Formal Methods and Models for Codesign, 1st ACM & IEEE Int. Conference MEMOCODE 2003. (pp. 47-48). Los Alamitos CA, USA: IEEE Computer Society Press.
Stuijk, S., Basten, A.A. & Ypma, J. (2003). A task-Level Concurrenc Analysis Tool (Extended Abstract). In J. Lilius, F. Balarin & R.J. Machado (Eds.), Application of Concurrency to System Design, 3rd International Conference, ACSD 2003, Proceedings. (pp. 237-238). Los Alamitos, CA, USA: IEEE Computer Society Press.
Stuijk, S., Basten, A.A. & Ypma, J. (2003). CAST - A Task-Level Concurrency Analysis Tool. In J. Lilius, F. Balarin & R.J. Machado (Eds.), Application of Concurrency to System Design, 3rd Int. Conference ACSD 03. (pp. 237-238). Los Alamitos CA, USA: IEEE Computer Society Press.
Stuijk, S., Ypma, J. & Basten, A.A. (2003). CAST - A Task-Level Concurrency Analysis Tool. In S. Vassiliadis, L.M.J. Florack, J.W.J. Heijnsdijk & A. van der Steen (Eds.), ASCI 2003, 9th Annual COnference of the Advanced School for Computing and Imaging, Proceedings. (pp. 106-113). Delft, the Netherlands: ASCI.
Basten, A.A., Benini, L., Chandrakasan, A., Lindwer, M., Liu, J., Min, R. & Zhao, F. (2003). Scaling into ambient intelligence. In N. Wehn & D. Verkest (Eds.), Proceedings of DATE 2003, March 3-7, Munich, Germany. (pp. 76-81).
Mousavi, M.R., Reniers, M.A., Basten, A.A. & Chaudron, M.R.V. (2003). Separation of concerns in the formal design of real-time shared data-space systems. In J. Lilius, F. Balarin & R.J. Machado (Eds.), Proceedings 3rd International Conference on Application of Concurrency to System Design (ACSD 2003, Guimaraes, Portugal, June 18-20, 2003). (pp. 71-81). Los Alamitos CA: IEEE Computer Society.
Fatemi, S.H., Ebrahimmalek, H., Kleihorst, R.P., Corporaal, H. & Jonker, P.P. (2003). Real-time Face Recognition on a Mixed SMID VLIW Architecture. In M. Schweizer (Ed.), Proceedings of the 4th PROGRESS Workshop on Embedded Systems 2003. Nieuwegein, the Netherlands: STW.
Fatemi, S.H., Kleihorst, R.P., Corporaal, H. & Jonker, P.P. (2003). Real-Time Face Recognition on a Smart Camera. Proceedings of Advanced Concepts for Intelligent Vision Systems 2003. (pp. 222-227).
Aa, T. van der, Jayapala, M., Barat, F., Corporaal, H., Catthoor, F. & Deconinck, G. (2003). Software transformations to reduce instruction memory power consumption using a loop buffer. ODES workshop (optimizations for DSPs and Embedded Systems).
Aa, T. van der, Jayapala, M., Barat, F., Deconinck, G., Lauwereins, R., Corporaal, H. & Catthoor, F. (2003). Instruction buffering exploration for low energy embedded processors. Proceedings of PATMOS 2003 conference. (pp. 409-419).
Barat, F., Jayapala, M., Aa, T. van der, Deconinck, G., Lauwereins, R. & Corporaal, H. (2003). Low Power Coarse-Grained Reconfigurable Instruction Set Processor. Proc. of the 13th International Conference on Field Programmable Logic and Applications (FPL 2003). (pp. 230-239).
Bekooij, M.J.G., Moreira, O., Poplavko, P., Mesman, B., Meerbergen, J. van, Duranton, M. & Steffens, E.F.M. (2003). Predictable Embedded Multiprocessor System Design. Proceedings of Philips Conference on DSP, 2003.
Beric, A., Haan, G. de, Meerbergen, J. van & Sethuraman, R. (2003). Design space exploration of a picute rate up-converter. Proc. of ASCI 2003. (pp. 246-251). Heijen, the Netherlands.
Beric, A., Haan, G. de, Meerbergen, J. van & Sethuraman, R. (2003). Towards an efficient high quality picture-rate up-converter. Proc. of IEEE International Conference on Image Processing. Barcelona, Spain.
Beric, A., Haan, G. de, Sethuraman, R. & Meerbergen, J. van (2003). Technique for reducing complexity of recursive motion estimation algorithms. Proceedings of IEEE Workshop on Signal Processing Sysems (SiPS).
Brockmeyer, E., Miranda, M., Catthoor, F. & Corporaal, H. (2003). Layer assignment techniques for low power in multi-layered memory organisations. Proceedings of DATE 2003. (pp. 1070-1075).
Caarls, W., Corporaal, H. & Jonker, P.P. (2003). Smartcam Design Framework. In M. Schweizer (Ed.), Proceedings of the 4th Progress Workshop 2003. (pp. 1-8). Nieuwegein, the Netherlands: STW.
Caarls, W., Jonker, P.P. & Corporaal, H. (2003). Benchmarks for SmartCam Development. Proceedings of ACIVS 2003. (pp. 81-86).
Garcea, G.S., Meijs, N.P. van der & Otten, R.H.J.M. (2003). Analytic Model for Area-Constrained OPtimal Repeater Insertion. Proceedings of the 7th IEEE Workshop on Signal Propagation on Interconnects. (pp. 127-130). Siena, Italy.
Garcea, G.S., Meijs, N.P. van der & Otten, R.H.J.M. (2003). Simultaneous Analytic Area and Power Optimization for Repeater Insertion. Proceedings of ICCAD 2003, November 9-13, San Jose, USA. (pp. 568-573).
Gheorghita, Valentin, Wong, W.F. & Florescu, O. (2003). EPIC - Adaptive EPIC Bridge. Proc. of the 14th International. (Vol. 21, pp. 92-97). Bucharest: CSCS14.
Greiner, J.C., Sethuraman, R., Meerbergen, J. van & Haan, G. de (2003). A cost-effective implementation of object-based motion estimation. IEEE Workshop on Signal Processing Sytems (SiPS) 2003.
Heikkinen, J., Rantanen, T., Cilio, A.G.M., Takala, J. & Corporaal, H. (2003). Evaluating template-based instruction compression on Transport Triggered Architectures. Proceedings of the International Workshop on System-on-Chip for Real-Time Applications. (pp. 192-195).
Heikkinen, J., Rantanen, T., Cilio, A.G.M., Takala, J. & Corporaal, H. (2003). Immediate Optimization for compressed Transport triggered Architecture Instructions. Proc. of Int. Symposium on System-on-Chip, Tampere, Finland. (pp. 65-69).
Huang, J., Voeten, J.P.M. & Geilen, M.C.W. (2003). Real-time property preservation in approximations of timed systems. Proc. of First ACM&IEEE Int. Conf. on Formal Methods and Models for Codesign (MEMOCODE'2003). (pp. 163-171). Mont Saint-Michel, France.
Huang, J., Voeten, J.P.M., Ventevogel, A. & Bokhoven, L.J. van (2003). Platform-independent design for embedded real-time system. Proc. of the Forum on Specifigation & Design Languages 2003. (pp. 318-329). Frankfurt, Germany: University of Frankfurt, Germany.
Huang, J., Voeten, J.P.M., Ventevogel, A. & Bokhoven, L.J. van (2003). Towards correctness-preserving synthesis for real-time software. Proc. of PROGRESS'03. (pp. 109-114). Utrecht, the Netherlands: Technology Foundation STW.
Kleihorst, R.P., Broers, H., Abbo, A.A., Ebrahimmalek, H., Fatemi, S.H., Corporaal, H. & Jonker, P.P. (2003). A SIMD-VLIW Smart Camera Architecture for Real-Time Face Recognition. Proceedings of the 14th ProRISC, Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2003) 26 - 27 November 2003, Veldhoven, the Netherlands. (pp. 114). Utrecht, the Netherlands: STW, Technology Foundation.
Leitao, J.A., Zhao, M. & Haan, G. de (2003). Content-adaptive video up-scaling for high-definition displays. Proceedings of IVCP 2003. (Vol. 5022).
Lindwer, M., Marculescu, D., Basten, A.A., Zimmermann, R., Marculescu, R., Jung, S. & Cantatore, E. (2003). Ambient intelligence visions and achievements : linking abstract ideas to real-world concepts. In N. Wehn & D. Verkest (Eds.), Proceedings of DATE 2003, March 3-7, Munich, Germany. (pp. 10-15).
Marchal, P., Bruni, D., Gomez, J.I., Benini, L., Pinuel, L., Catthoor, F. & Corporaal, H. (2003). SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms. Proceedings of DATE 2003. (pp. 516-521).
Papanikolaou, A., Miranda, M., Catthoor, F., Corporaal, H., Man, H. de, de Roest, D., Stucchi, M. & Maex, K. (2003). Interconnect and Architecture Planning: Global interconnect trade-off for technology over memory modules to application level: case study. Proceedings of International Workshop on System-level interconnect prediction, April 2003.
Pastrnak, M., Poplavko, P., With, P.H.N. de & Meerbergen, J. van (2003). On resource estimation of MPEG-4 video decoding for a multiprocessor architecture. Proceedings 4th PROGRESS Symposium on Embedded Systems (Nieuwegein, The Netherlands, October 22, 2003). (pp. 185-193). Utrecht: STW.
Poplavko, P. & Pastrnak, M. (2003). Modeling Predictable Multiprocessor Performance for Video Decoding. On the design of multimedia architectures: proc. of a one-day workshop. (pp. 133-136). Eindhoven, the Netherlands: TU Eindhoven.
Poplavko, P., Basten, A.A., Bekooij, M.J.G., Meerbergen, J. van & Mesman, B. (2003). Task-level Timing Models for Guaranteed Performance in Multiprocessor Networks -on-Chip. Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems. (pp. 63-72). San Jose, CA, USA: ACN.
Poplavko, P., Pastrnak, M., Basten, A.A., With, P.H.N. de & Meerbergen, J. van (2003). Mapping MPEG-4 Video Object Shape-Texture Decoding onto an Multiprocessor Network-on-Chip. Proceedings 14th Workshop on Circuits, Integrated systems and Signal Processing (ProRisc). (pp. 139-147).
Rijpkema, E., Goossens, K.G.W., Radulescu, A., Dielissen, J.T.M.H., Meerbergen, J. van, Wielage, P. & Waterlander, E. (2003). Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. Proceedings of DATE 2003.
Terechko, A., Thenaff, E. le & Corporaal, H. (2003). Cluster assignment of global values for clustered VLIW processors. Proceedings of CASES conference 2003. (pp. 32-40).
Terechko, A., Thenaff, E. le, Garg, M., Eijndhoven, J.T.J. van & Corporaal, H. (2003). Inter-cluster communication models for clustered VLIW processors. Proceedings of the Ninth International Symposium on High Performance Computer Architecture. (pp. 354-364).
Westra, H.J.L., Jongeneel, D.-J., Otten, R.H.J.M. & Visweswariah, C. (2003). Time budgeting in a wireplanning context. Proceedings of DATE 2003, March 3-7, Munich, Germany. (pp. 10436-10441).
Wittebrood, R.B & Haan, G. de (2003). Efficient image segmentation and its application to motion estimation. Proceedings of IVCP 2003. (Vol. 5022).
Wittebrood, R.B, Haan, G. de & Lodder, R. (2003). Tackling occlusion in scan rate conversion systems. Digest of the ICCE'03. (pp. 344-345).
Zhao, M. & Haan, G. de (2003). Content adaptive video up-scaling. Proc. ASCI 2003. (pp. 151-156).
Zhao, Q., Mesman, B. & Corporaal, H. (2003). Limited address range architecture for reducing code size in embedded systems. Proceedings of SCOPES conference, 2003.

2002

Otten, R.H.J.M., Camposano, R. & Groeneveld, P.R. (2002). Design Automation for Deepsubmicron: present and future. Proc. of DATE 2002. (pp. 650-657). Paris.
Reymen, I.M.M.J., Kroes, P. & Basten, A.A. (2002). Modelling the role of the design context in the design process : A domain-independent approach. In D. Durling & J. Shackleton (Eds.), Proceedings Common Ground, Design Research Society International Conference. (pp. 917-927). Stoke-on-Trent, UK: Staffordshire University Press.
Haan, G. de & Kettenis, J. (2002). System-on-Silicon for High Quality Display Format Conversion and Video Enhancement. Proceeings of ISCE 2002. (pp. E1-E6).
Haan, G. de & Lodder, R. (2002). De-interlacing of video data using motion vectors and edge information. Digest of the ICCE'02. (pp. 70-71). Los Angeles, USA.
Mousavi, M.R., Russello, G., Chaudron, M.R.V., Reniers, M.A., Basten, A.A., Corsaro, A., Shukla, S.K., Gupta, R.K. & Schmidt, D.C. (2002). Using Aspect-GAMMA in the design of embedded systems (Extended abstract). Proceedings Seventh Annual IEEE International High Level Design Validation and Test Workshop (HLDVT'02, Cannes, France, October 27-29, 2002). (pp. 69-74). Los Alamitos CA, USA: IEEE Computer Society.
Mousavi, M.R., Russello, G., Chaudron, M.R.V., Reniers, M.A., Basten, A.A., Corsaro, A., Shukla, S.K., Gupta, R.K. & Schmidt, D.C. (2002). Aspects + GAMMA = AspectGAMMA : A formal framework for aspect-oriented specification. Workshop Early Aspects : Aspect-Oriented Requirements Engineering and Architecture Design, 1st International Conference on Aspect-Oriented Software Development (AOSD 2002, Enschede, The Netherlands, April 22-26, 2002).
Mousavi, M.R., Russello, G., Chaudron, M.R.V., Basten, A.A. & Reniers, M.A. (2002). Separation of quality concerns in the development of distributed real-time systems. Proceedings 3rd PROGRESS Workshop on Embedded Systems (Utrecht, The Netherlands, October 24, 2002). (pp. 124-127). Utrecht, the Netherlands: STW.
Goossens, K.G.W. & Gangwal, O.P. (2002). The cost of communication protocols and coordination languages in embedded systems. In F. Arbab & C. Talcott (Eds.), Coordination languages and models : Proceedings of the 5th International Conference Coordination Models and Languages7th International Conference (COORDINATION 2002) 20-23 April 2002 York, UK. (Lecture Notes in Computer Science, Vol. 2315, pp. 174-190). Berlin: Springer Verlag.
Goossens, K.G.W., Meerbergen, J. van, Peeters, A.M.G. & Wielage, P. (2002). Networks on Silicon: Combining Best-Effort and Guaranteed Services. Proc. of the DATE conf. (pp. 423-425). Parijs.
Beric, A., Sethuraman, R., Meerbergen, J. van & Haan, G. de (2002). Algorithm/Architecture Co-Design of a Picture-Rate Up-conversion Module. Proc. of ProRISC 2002. (pp. 203-208). Utrecht: STW Technology Foundation.
Braspenning, R. & Haan, G. de (2002). Efficient Motion Estimation with Content-Adaptive Resolution. Proceedings of ISCE 2002. (pp. E29-E-34).
Braspenning, R., Haan, G. de & Hentschel, C. (2002). Complexity scalable motion estimation. Proc. of SPIE: Visual Communications and Image Processing 2002. (Vol. 4671, No. 1/2, pp. 442-453). San Jose, CA, USA.
Bruijn, F.J., Bruls, W.H.A., Burazerovic, D. & Haan, G. de (2002). Efficient video coding integrating MPEG-2 and picture-rate conversion. Digest of the ICCE'02. (pp. 338-339). Los Angeles, USA.
Cilio, A.G.M. & Corporaal, H. (2002). Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation. Conference on Compiler Construction, Grenoble, France, April 2002. Grenoble, France.
Gomez, J.I., Marchal, P., Bruni, D., Benini, L., Prieto, M., Catthoor, F. & Corporaal, H. (2002). Scenario-based SDRAM-Energy-Aware Scheduling for Dynamic Multi-Media Applications on Multi-Processor Platforms. Workshop on Application Specific Processors (WASP), November 2002, Istanbul. Istanbul.
Groeneveld, P.R. (2002). Physical Design Challenges for Billion Transistor Chips. Proc. ICCD 2002. (pp. 78-84).
Groeneveld, P.R. (2002). Tools or Users: which is the bigger bottleneck? Proc. of DAC 2002. (pp. 76-77). New Orleans.
Heikkinen, J., Takala, J., Cilio, A.G.M. & Corporaal, H. (2002). On efficiency of Transport Triggered A5rchitectures in DSP applications. WSEAS Int. Conference on Signal Processing, Robotics and Automation, Cadiz, Spain, June 2002. Cadiz, Spain.
Huang, J., Voeten, J.P.M., Putten, P.H.A. van der, Ventevogel, A., Niesten, R. & Maaden, W. van der (2002). Performance Evaluation of Complex Real-time Systems: A case Study. In F. Karelse (Ed.), Proc. of the PROGRESS workshop 2002. (pp. 77-82). Utrecht: STW Technology Foundation.
Huang, J., Verschueren, A.C., Aalderink, H.A. & Lukkien, J.J. (2002). A calculus for mobile network systems. In C. George & H. Miao (Eds.), Formal Methods and Software Engineering (Proceedings ICFEM 2002, Shanghai, China, October 21-25, 2002). (Lecture Notes in Computer Science, Vol. 2495, pp. 226-230). Berlin: Springer-Verlag.
Jayapala, M., Barat, F., Aa, T. van der, Deconinck, G., Catthoor, F. & Corporaal, H. (2002). Clustered L0 Buffer Organization for Low Energy Embedded Processors. Workshop on Application Specific Processors (WASP), nov. 2002, Istanbul. Istanbul.
Jayapala, M., Barat, F., Op de Beeck, P., Catthoor, F., Deconinck, G. & Corporaal, H. (2002). A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. PATMOS (Power And Timing Modelling Optimization Simulation) conference, 2002.
Klompenhouwer, M.A., Haan, G. de & Beuker, R.A. (2002). Subpixel Image Scaling for Color Matrix Displays. Digest of the SID'02. (pp. 176-180). Boston, Massachusetts, USA.
Leijten-Nowak, K. & Meerbergen, J. van (2002). Embedded Reconfigurable Logic Core for DSP Applications. Proc. of Field Programmable Logic and Applications Conference. (pp. 89-101). Montpellier.
Maex, K., Beyne, E., Catthoor, F., Corporaal, H. & Man, H. de (2002). Exploiting wiring hierarchy and system design to surpass the interconnect red brick wall. Solid State Technology, 2002.
Papanikolaou, A., Miranda, M., Catthoor, F., Corporaal, H., Man, H. de, de Roest, D., Stucchi, M. & Maex, K. (2002). Interconnect exploration for future wire dominated technologies. System Level Interconnect Prediction workshop, San Diego (USA), April 2002. San Diego, USA.
Puttenstein, J.G., Heynderickx, I.E.J. & Haan, G. de (2002). Objective evaluation of noise reduction performance in TV-systems. Proc. of IEEE Internationa Conference on Image Processing 2002. (pp. 69-72). Rochester, New York, USA.
Roos, S., Corporaal, H. & Lamberts, R. (2002). Clustering on the move. 4th International Conference on Massively Parallel Computing Systems, April 2002.
Rutten, M.J., Eijndhoven, J.T.J. van, Pol, E-J.D., Jaspers, E.G.T., Wolf, P. v d, Gangwal, O.P. & Timmer, A. (2002). Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing. Proceedings workshop on Parallel and Distributed Computing in Image Processing, Video Processing and Multimedia, PDIVM 2002. (pp. 130-130). Fort Lauderdale, Florida, USA.
Wittebrood, R.B & Haan, G. de (2002). Feature point selection for object-based motion estimation on a Programmable Device. Proc. of SPIE: Visual Communications and Image Processing 2002. (Vol. 4671, No. 2/2, pp. 687-697). San Jose, CA, USA.
Zhao, M., Leitao, J.A. & Haan, G. de (2002). Towards an Overview of Spatial Up-conversion Techniques. Proc. of ISCE 2002. (pp. E13-E16).
Zhao, Q., Mesman, B. & Basten, A.A. (2002). Practical Instruction Set Design and Compiler Retargetability Using Static resource Models. In C. Delgado Kloos & J. da Franca (Eds.), Proceedings of Design, Automation and Test in Europe 2002. (pp. 1021-1026). Los Alamitos, CA USA: IEEE Computer Society Press.

2001

Otten, R.H.J.M. & Garcea, G.S. (2001). Are wires plannable? Proceedings of the 2001 Int. Workshop on System-level interconnect prediction. (pp. 59-66).
Aalst, W.M.P. van der & Basten, A.A. (2001). Identifying commonalities and differences in object life cycles using behavioral inheritance. In J.M. Colom & M. Koutny (Eds.), Proceedings of the 22nd International Conference on Application and Theory of Petri Nets (ICATPN 2001) 25-29 June 2001, Newcastle upon Tyne, UK. (Lecture Notes in Computer Science, Vol. 2075, pp. 32-52). Berlin: Springer.
Verhoeven, R., Huang, J. & Lukkien, J.J. (2001). Network middleware and mobility. In F. Karelse (Ed.), Proceedings 2nd PROGRESS Workshop on Embedded Systems (Utrecht, The Netherlands, October 18, 2001). (pp. 287-292). Utrecht: STW.
Mesman, B., Timmer, A.H., Meerbergen, J. van & Jess, J.A.G. (2001). Constraint analysis for DSP code generation. In G. De Micheli, R. Ernst & W. Wolf (Eds.), Readings in Hardware/Software Co-design. (pp. 485-498).
Basten, A.A. & Bosnacki, D. (2001). Enhancing partial-order reduction via process clustering. Proceedings of the 16th IEEE International Conference on Automated Software Engineering (ASE 2001, San Diego CA, USA, November 26-29, 2001). (pp. 245-253). Los Alamitos, CA, USA: IEEE Computer Society Press.
Basten, A.A. & Hoogerbrugge, J. (2001). Efficient Execution of Process Networks. In A. Chalmers, M. Mirmehdi & H. Muller (Eds.), Proceedings of Communicating Process Arcitectures 2001. (pp. 1-14). Amsterdam: IOS Press.
Meerbergen, J. van (2001). Communication Architectures for Deep-submicron VLSI systems. Summer school on Application-Specific Multi-Processor SoC. (Vol. part V, pp. 1-11).
Meerbergen, J. van (2001). Networks-on-Silicon: A New Architecture for on-chip Communication. In R.H.J.M. Otten prof.dr.ir. (Ed.), Holst Symposium TU Eindhoven. Eindhoven: University Press , TU Eindhoven.
Haan, G. de & Klompenhouwer, M.A. (2001). Temporal espects of emerging displays. IEEE Digest of the ICCE 2001, June 2001, Los Angeles, USA. (pp. 42-43).
Haan, G. de (2001). Signal processing for enhaced image representation. Dortmunder Fernseh Seminar. (pp. 53-64). Dortmund.
Corporaal, H. (2001). Embedded processor Design using Transport Triggered Architectures. In R.H.J.M. prof.dr.ir. Otten (Ed.), Holst symposium 2001. (pp. 25-34). Eindhoven: University press TU Eindhoven.
Pineda de Gyvez, J. & Pineda de Gyvez, J. (2001). Yield modeling and BEOL fundamentals. Proceedings of the 2001 International Workshop on System Level Interconnect Prediction, Sonoma CA, USA, March 2001. (pp. 135-163). New York: ACM.
Alba Pinto, C.A., Mesman, B. & Jess, J.A.G. (2001). Constraint Satisfaction for Relative Location Assignment and Scheduling. Proceedings of the Int. Conference on Computer Aided Design. (pp. 384-390). San Jose.
Alba Pinto, C.A., Mesman, B., Eijk, C.A.J. van & Jess, J.A.G. (2001). Constraint satisfaction for storage files with fifos or stacks during scheduling. Proceedings DATE conference 2000. (pp. 824-824). Munchen.
Arnold, M. & Corporaal, H. (2001). Designing Domain-Specific Processors. Proc. of the 9th Int. Workshop on Hardware-Software Co-Design, CODES 01. (pp. 61-66).
Bekooij, M.J.G., Mesman, B., Meerbergen, J. van & Jess, J.A.G. (2001). Tightly coupled operation assignment and scheduling for vliw processors with facts. Proceedings of the SCOPE workshop 2001.
Bekooij, M.J.G., Dielissen, J.T.M.H., Harmsze, F., Sawitzki, S., Huisken, J., Werf, A. van der & Meerbergen, J. van (2001). Power-efficient application-specific VLIW processor for turbo decoding. IEEE International Solid-State Circuits Conference ; 48 (San Francisco, Calif.) : 2001.02.05-07. (Digest of technical papers, Vol. 44, pp. 180-181). Piscataway: IEEE.
Bellers, E.B., Weert, I. de, Haan, G. de & Heynderickx, I.E.J. (2001). Optimal television scanning format for CRT-displays. IEEE Digest of the ICCE'01. (pp. 48-49).
Cilio, A.G.M. & Corporaal, H. (2001). Code positioning for VLIW architectures. Proc. of HPCN 2001. (pp. 332-343).
Dielissen, J.T.M.H., Meerbergen, J. van, Bekooij, M.J.G., Harmsze, F., Sawitzki, S., Huisken, J. & Werf, A. van der (2001). Power-efficient layered turbo decoder processor. Proc. of the DATE conference 2001. (pp. 246-251).
Groeneveld, P.R. (2001). Gain Based Synthesis. Part of tutorial Design Closure for Ultra-deep Submicron Design. Separate booklet at ASP-DAC 01. (pp. 1-25). Yokohama Japan.
Groeneveld, P.R. (2001). RTL-down methodologies for design closure. Proc. of the EDP 2001, session 5 - 1, pagina 20. (pp. 20-20). Monterey, CA.
Hamalainen, P., Hannikainen, M., Hamalainen, T., Corporaal, H. & Saarinen, J. (2001). Implementation of Encryption Algorithms on Transport Triggered Architectures. Proc. of ISCAS 2001.
Jacobs, E.T.A.F. (2001). A path-based method for statistical delay calculation dealing with correlations due to reconverging paths. Workshop notes of the IWLS 2001. (pp. 322-327).
Klompenhouwer, M.A. & Haan, G. de (2001). Color error diffusion: Accurate luminance from coarsely quantized displays. Digest of the SID 2001. (pp. 214-217). San Jose, CA.
Leijten-Nowak, K. & Meerbergen, J. van (2001). Applying the Adder Inverting Property in the Design of Cost-Efficient Reconfigurable Logic. Proc. of the 44th Midwest Symposium on Circuits and Systems. (pp. 434-437).
Mertens, M.J.W. & Haan, G. de (2001). Motion Vector field improvement for picture rate conversion with reduced Halo. Proc. of the SPIE/IST VCIP, San Jose, CA. (pp. 352-362).
Mostert, S., Cossement, N., Meerbergen, J. van & Lauwereins, R. (2001). "DF*: Modeling Dynamic Process Creation and Events for Interactive Multimedia Applications. Proc. of the 12th Int. Workshop on Rapid Systems Prototyping. (pp. 122-127).
Naidu, S.R. & Jacobs, E.T.A.F. (2001). Minimizing stand-by leakage power in static CMOS circuits. Proc. of the DATE conference 2001. (pp. 370-376).
Naidu, S.R. (2001). An impulse-train approach to statistical timing analysis. Proc. of the Int. Workshop on Logic and Synthesis 2001. (pp. 328-331).
Pelagotti, A. & Haan, G. de (2001). A new high quality algorithm for video format up-conversion. Proceedings of the ICIP2001. (pp. 375-378).
Poplavko, P., Leijten-Nowak, K. & Meerbergen, J. van (2001). Placement algorithms for datapath-oriented FPGAs. Proc. of the ProRisc Conference, nov. 2001.
Wittebrood, R.B & Haan, G. de (2001). Real-time recursive motion segmentation of video data. IEEE Digest of the ICCE 2001, June 2001, Los Angeles. (pp. 288-289).
Zhao, Q. & Mesman, B. (2001). Static Resource Models of Highly Encoded Instruction Sets. Proceedings of the ProRisc'01 (CD-rom). (pp. 588-594). Veldhoven.
Zhao, Q., Basten, A.A., Mesman, B., Eijk, C.A.J. van & Jess, J.A.G. (2001). Static Resource Models of Instruction Sets. Proceedings of the 14th Int. Symposium on System Synthesis ISSS 2001. (pp. 159-164). New York USA: ACM Press.

2000

Otten, R.H.J.M. & Stravers, P. (2000). Challenges in physical chip design. Proceedings ICCAD2000. (pp. 84-91). San Jose, CA, USA.
Otten, R.H.J.M. (2000). What is a floorplan. Proc. 2000 Internation symposium on physical design. (pp. 201-206). San Diego, CA, USA.
Otten, R.H.J.M., Jongeneel, D.-J. & Brayton, R.K. (2000). Area control and search space limitations for technology mapping. Proceedings of the 37th Design Automation Conference. (pp. 86-91). Los Angelos.
Geilen, M.C.W. & Dams, D.R. (2000). An on-the-fly tableau construction for a real-time temporal logic. In M. Joseph (Ed.), Formal techniques in real-time and fault-tolerant systems : 6th international symposium, Pune, India, September 20 - 22, 2000 ; proceedings / FTRTFT 2000. (Lecture Notes in Computer Science, Vol. 1926, pp. 276-290). Berlin: Springer Verlag.
Geilen, M.C.W. (2000). Model-Checking in Simulations of Distributed Systes. In D.F.P. Moeller (Ed.), Proceedings of 12th European Simulation Symposium ESS 2000. (pp. 606-611). Hamburg, Germany: Society for Computer Simulation International.
Haan, G. de (2000). Progress in motion estimation for video format conversion. IEEE, Digest ICCE'2000. (pp. 50-51). Los Angelos.
Haan, G. de (2000). Video processing for multimedia systems. Proc. IEEE Symposium Information Theory in the Benelux. (pp. 189-198). Wassenaar.
Corporaal, H. (2000). Embedded Processor Design Using Transport Triggered Architectures. Proc. of Int. Workshop on Spectral Techniques and Logic Design for Future Digital Systems. (pp. 469-482).
Alba Pinto, C.A., Mesman, B. & Eijk, C.A.J. van (2000). Address satisfaction for storage files with fifos or stacks during scheduling of DSP algorithms. Proc. XIII Symposium on Integrated Circuits and Systems Design, SBCCI. (pp. 107-112). Los Alamitos, CA: IEEE Computer Society.
Alba Pinto, C.A., Eijk, C.A.J. van, Mesman, B. & Jess, J.A.G. (2000). Satisfaction of constraints for storage files with fifos or stacks during scheduling. In J.P. Veen & H. Varwijk (Eds.), CD-ROM: Book of Abstracts of the ProRISC/IEEE workshop on Circuits, Systems and Signal Processing 2000. (pp. 171-180). Veldhoven: STW Technology Foundation, Utrecht..
Bekooij, M.J.G., Mesman, B., Meerbergen, J. van & Jess, J.A.G. (2000). Constraint analysis for operation assignment and scheduling in FACTS. Proc. International Conference on Signal Processing Applications & Technology, 16-19 oktober 2000, Dallas, Texas USA. Dallas.
Bekooij, M.J.G., Mesman, B., Meerbergen, J. van & Jess, J.A.G. (2000). Constraint analysis for operation assignment in FACT. Proc. ProRISC workshop. (pp. 229-236).
Bellers, E.B. & Haan, G. de (2000). Majority selection de-interlacing; An advanced motion-compensated spatio-temporal interpolation technique for interlaced video. Electronic Imaging 2000, Image and Video Communications and Processing. (Vol. 3974, pp. 386-395). San Jose.
Bellers, E.B. & Haan, G. de (2000). Towards an optimal television display format. Proc. ICIP 2000. (Vol. I of III, pp. 749-752). Vancouver.
Berkelaar, M.R.C.M., Jacobs, E.T.A.F. & Puig, J.M. (2000). Sources and quantification of delay variations in a 250nm CMOS digital cell library. Proc. International Workshop on Logic Synthesis 2000. (pp. 335-339). Dana Point, CA, USA.
Eijk, C.A.J. van (2000). Constraint driven design space exploration for signal processing. Proc. Signal Processing Symposium SPS 2000. (pp. P.I.1.1-P.I.1.4). Hilvarenbeek, Nederland.
Harmsze, F., Timmer, A.H. & Meerbergen, J. van (2000). Memory arbitration and cache management in stream-based system. Proc. DATE 2000. (pp. 257-262). Paris, France.
Jacobs, E.T.A.F. & Berkelaar, M.R.C.M. (2000). Gate sizing using a statistical delay model. Proc. DATE 2000. (pp. 283-290). Paris, France.
Jacobs, E.T.A.F. & Berkelaar, M.R.C.M. (2000). Improving the accuracy of statistical delay calculation. Proc. International Workshop on Logic Synthesis 2000. (pp. 297-301). Dana Point, CA, USA.
Kastrup, B., Trum, J.J.C., Moreira, O., Hoogerbrugge, J. & Meerbergen, J. van (2000). Compiling applications for ConCISe : an example of automatic HW/SW partitioning and synthesis. In R.W. Hartenstein & H. Grünbacher (Eds.), Field-Programmable Logic and Applications : The Roadmap to Reconfigurable Computing (Proceedings 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000). (Lecture Notes in Computer Science, Vol. 1896, pp. 695-706). Berlin: Springer-Verlag.
Kisuki, T., Corporaal, H. & Knijnenburg, P.M.W. (2000). The effect of process switches on branch prediction accuracy. Proceedings of the 5th Annual Conference of the Advanced School for Computing and Imaging, Heijen. (pp. 81-88).
Klompenhouwer, M.A. & Haan, G. de (2000). Optimally reducing motion artifacts in plasma displays. SID '00 Digest. (pp. 388-391). Long Beach.
Manniesing, R., Karkowski, I. & Corporaal, H. (2000). Automatic SIMD Parallelization of Embedded Applications based on Pattern Recognition. Euro-Par 2000 parallel processing : 6th International Euro-Par Conference, Munich, Germany, August/September 2000 : proceedings. (pp. 349-356). New York: Springer.
Manniesing, R., Karkowski, I. & Corporaal, H. (2000). Automatic SIMD Parallelization of Embedded Applications based on Pattern Recognitiion. Proceedings of Euro-par 2000, Munich, Germany.
Mertens, M.J.W. & Haan, G. de (2000). A block based motion estimator capable of handling occlusions. Proc. MVA2000: IAPR Workshop on Machine Vision Applications. (pp. 529-532). Tokyo.
Naidu, S.R. & Berkelaar, M.R.C.M. (2000). Minimizing leakage power in CMOS circuits operating in stand-by mode. Proc. International Workshop on Logic Synthesis 2000. (pp. 231-235). Dana Point, CA, USA.
Poplavko, P., Eijk, C.A.J. van & Basten, A.A. (2000). Constraint analysis and heuristic scheduling methods. In J.P. Veen (Ed.), Proc. ProRISC 2000. (pp. 447-453). Utrecht, the Netherlands: STW Technology Foundation.
Schot, H.J.M. & Corporaal, H. (2000). Automated design of an ASIP for image processing applications. In A. Bode (Ed.), Euro-PAR, parallel processing : international conference : proceedings, 6th , Munich, Germany, August 29 - September 1, 2000. (Lecture Notes in Computer Science, Vol. 1900, pp. 1105-1109). Berlin: Springer.
Stanca, M., Corporaal, H. & Karkowski, I. (2000). Power consumption reduction methods using loop transformations. Proceedings of the 18th IASTED Int. Conference on Applied Informatics (AI 2000). (pp. 278-284). Februari 2000 Innsbruck, Austria.
Strik, M.T.J., Timmer, A.H., Meerbergen, J. van, Waterlander, E., Harmsze, F., Vaassen, A., Sevat, L., Oosterhuis, M., Rootselaar, G.J. van, Herten, H. van, Jaspers, E.G.T., Janssen, J., Essink, G. & Leijten, J.A.J. (2000). Heterogeneous multi-processor for the management of real-time video & graphics streams. Proc. ISSCC 2000, TP 14.8. (pp. 244-245).
Tavares, R. & Berkelaar, M.R.C.M. (2000). Logic circuits based on or-binary decision diagrams. Proc. International Workshop on Logic Synthesis 2000. (pp. 91-95). Dana Point, CA USA.
Wittebrood, R.B & Haan, G. de (2000). Second generation video format conversion in a programable device. IEEE, Digest ICCE'2000. (pp. 230-231). Los Angeles.
Zhao, Q., Eijk, C.A.J. van, Alba Pinto, C.A. & Jess, J.A.G. (2000). Register binding for predicated execution in DSP applications. Proc. SBCCI2000, 13th Symposium on Integrated Circuits and Systems Design. (pp. 113-118). Manaus, Amazonas, Brazil.

1999

With, P.H.N. de, Jaspers, E.G.T., Timmer, A.H. & Meerbergen, J. van (1999). A video display processing platform for future TV concepts. Digest International Conference on Consumer Electronics (ICCE). (pp. 208-209). Los Angeles, CA.
Mesman, B., Alba Pinto, C.A. & Eijk, C.A.J. van (1999). Efficient scheduling of DSP code on processors with distributed register files. In F.J. Kurdahi (Ed.), Proc. International Symposium on System Synthesis. (pp. 100-106). Los Alamitos, CA: IEEE Computer Society.
Mesman, B., Eijk, C.A.J. van, Alba Pinto, C.A., Bekooij, M.J.G., Meerbergen, J. van & Jess, J.A.G. (1999). Constraint analysis for code generation: basic techniques and applications in FACTS. In P. Marwedel (Ed.), Proc. SCOPES '99, 4th International Workshop on Software and Compilers for Embedded Systems. (pp. 3.1-3.35). St. Goar, Germany.
Geilen, M.C.W. (1999). Formal Models for Encapsulation, Structure and Hierarchy in Distributed Systems. In J.P. Veen (Ed.), Proceedings of the 10th Annual Workshop on Circuits, Systems and Signal Processing. (pp. 155-166). Utrecht: STW Technology Foundation.
Alba Pinto, C.A., Mesman, B. & Eijk, C.A.J. van (1999). Register file capacity satisfaction during scheduling. In J.P. Veen (Ed.), Proc. ProRISC 99, 10th Annual Workshop on Circuits, Systems and Signal Processing. (pp. 1-8). Utrecht, Netherlands: STW, Technology Foundation.
Alba Pinto, C.A., Mesman, B. & Eijk, C.A.J. van (1999). Register files constraint satisfaction during scheduling of DSP code. In B. Werner (Ed.), Proc. XII Symposium on Integrated Circuits and Systems Design. (pp. 74-77). Los Alamitos, CA: IEEE Computer Society.
Arnold, M. & Corporaal, H. (1999). Automatic detection of recurring operation patterns. Proceedings of the Seventh International Workshop on Hardware/Software Codesign : (CODES '99), May 3 - 5, 1999, Rome, Italy. (pp. 22-26). New York: ACM.
Boekhold, M., Karkowski, I. & Corporaal, H. (1999). Transforming and Prallelizing ANSI C Programs using Pattern Recognition. In Peter Sloot ... (ed.) (Ed.), High performance computing and networking : 7th international conference / HPCN Europe 1999, Amsterdam, The Netherlands, April 12- 4, 1999 ; Peter Sloot ... (ed.). (pp. 673-690). Springer.
Boekhold, M., Karkowski, I., Corporaal, H. & Cilio, A.G.M. (1999). A Programmable ANSI C Code Transformation Engine. Proc. of ETPs99, Amsterdam, March 1999.
Cilio, A.G.M. & Corporaal, H. (1999). A Linker for Effective Whole-program Optimizations. Procd. of High Performance Computing and Networking Conference, April 1999, Amsterdam, the Netherlands.
Cilio, A.G.M. & Corporaal, H. (1999). Floating Point to Fixed Point Conversion of C Code. Proc. of ETAPs99, Amsterdam, March 1999.
Eijk, C.A.J. van, Jacobs, E.T.A.F., Mesman, B. & Timmer, A.H. (1999). Identification and exploitation of symmetries in DSP algorithms. In D. Borrione & R. Ernst (Eds.), Proc. Design Automation and Test in Europe (DATE'99). (pp. 602-608). Los Alamitos, CA: IEEE Computer Society.
Gonzalez, O.A., Han, G., Pineda de Gyvez, J. & Edgar, . (1999). CMOS cryptosystem using a Lorenz chaotic oscillator. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999, ISCAS '99, 30 May - 2 June 1999, Orlando, Florida. (Vol. 5, pp. 442-445). New York: IEEE.
Jacobs, E.T.A.F. & Berkelaar, M.R.C.M. (1999). Comparison of gate sizing formulations and solving methods. In J.P. Veen (Ed.), Proc. ProRISC 99, 10th Annual Workshop on Circuits, Systems and Signal Processing. (pp. 209-218). Utrecht, Netherlands: STW, Technology Foundation.
Jacobs, E.T.A.F. & Berkelaar, M.R.C.M. (1999). Estimation of an upper bound on the maximum power of CMOS circuits using linear programming. In J. Sparso & D. Doudris (Eds.), Proc. Power Area and Timing Modeling, Optimization and Simulation Workshop. (pp. 335-344). Patras, Greece: Democritus University of Thrace.
Jacobs, E.T.A.F. & Berkelaar, M.R.C.M. (1999). Gate sizing using a statistical delay model. In F. Somenzi (Ed.), Proc. IEEE/International Workshop on Logic Synthesis - IWLS'99. (pp. 307-311). University of Colorado.
Kastrup, B., Meerbergen, J. van & Nowak, K. (1999). Seeking (the right) problems for the solutions of reconfigurable computing. Proc. FPL'99, 9th International Workshop on Field-Programmable Logic and Applications. (pp. 520-525). Berlin-Heidelberg, Germany.
Kisuki, T., Corporaal, H. & Knijnenburg, P.M.W. (1999). Branch History Register Cache. Proc. of ACM ICS Workshop on Scheduling Algorithms for Parallel and Distributed Computing, 1999.
Nier, R.P. de (1999). Property checking of PI-bus modules. In J.P. Veen (Ed.), Proc. ProRISC 99, 10th Annual Workshop on Circuits, Systems and Signal Processing. (pp. 343-354). Utrecht, Netherlands: STW, Technology Foundation.
Tavares, R. & Berkelaar, M.R.C.M. (1999). Reducing switching activity in logic circuits. Proc. IEEE/International Workshop on Logic Synthesis - IWLS'99. (pp. 312-315).
Tavares, R., Eijk, C.A.J. van & Berkelaar, M.R.C.M. (1999). BDD techniques to reduce switching activity in logic circuits. In J.P. Veen (Ed.), Proc. ProRISC 99, 10th Annual Workshop on Circuits, Systems and Signal processing. (pp. 497-502). Utrecht, Netherlands: STW, Technology Foundation.
Timmer, A.H., Harmsze, F., Leijten, J.A.J., Strik, M.T.J. & Meerbergen, J. van (1999). Guaranteeing on- and off-chip communication in embedded systems. IEEE Computer Society Workshop on VLSI'99. (pp. 93-98). Orlando, FL.
Zhao, Q. & Eijk, C.A.J. van (1999). Register binding for DSP code containing predicated execution. In J.P. Veen (Ed.), Proc. ProRISC 99, 10th Annual Workshop on Circuits, Systems and Signal Processing. (pp. 611-618). Utrecht, Netherlands: STW, Technology Foundation.

1998

Mesman, B., Strik, M.T.J., Timmer, A.H., Meerbergen, J. van & Jess, J.A.G. (1998). A constraint driven approach to loop pipelining and register binding. In A. Kunzmann (Ed.), Proc. Conference on Design, Automation and Test in Europe, DATE. (pp. 377-383). Los Alamitos, CA: IEEE Computer Society.
Meerbergen, J. van, Timmer, A.H., Leijten, J.A.J., Harmsze, F. & Strik, M.T.J. (1998). Experience with system level design for consumer ICs. In A. Smailagic, R. Broderson & H. De Man (Eds.), Proc. IEEE-CS Workshop on VLSI. (pp. 17-22). Los Alamitos, CA: IEEE Computer Society.
Arts, H.M.A.M. & Berkelaar, M.R.C.M. (1998). Combining logic synthesis and retiming. Proc. International Workshop on Logic Synthesis. (pp. 136-139).
Eijk, C.A.J. van & Janssen, G.L.J.M. (1998). On the efficiency of learning techniques for combinational checking. Proc. International Workshop on Logic Synthesis. (pp. 40-43).
Eijk, C.A.J. van (1998). Sequential equivalence checking without state space traversal. In A. Kunzmann (Ed.), Proc. Conference on Design, Automation and Test in Europe, DATE. (pp. 618-623). Los Alamitos, CA: IEEE Computer Society.
Eijk, C.A.J. van, Mesman, B. & Timmer, A.H. (1998). Utilizing symmetries in DSP algorithms to improve constraint analysis. In J.P. Veen (Ed.), Proc. ProRisc/IEEE and STW's CSSP98/SAFE98. (pp. 155-159). Utrecht, Netherlands: IEEE European Chapter, Stichting Technische Wetenschappen.
Eijndhoven, J.T.J. van & Sijstermans, F.W. (1998). Novel multimedia instruction capabilities in VLIW media processors. Proc. HotChips Symposium. (pp. 13-15). Stanford, CA: IEEE Computer Society.
Jacobs, E.T.A.F. & Berkelaar, M.R.C.M. (1998). A continuous nonlinear constrained optimization approach for maximum power estimation for CMOS circuits. In J.P. Veen (Ed.), Proc. ProRISC/IEEE and STW's CSSP98/SAFE98. (pp. 235-242). Utrecht, Netherlands: IEEE European Chapter, Stichting Technische Wetenschappen.
Jacobs, E.T.A.F. & Berkelaar, M.R.C.M. (1998). A linear programming approach for the estimation of an upper bound on the maximum power of CMOS circuits. Proc. International Workshop on Logic Synthesis. (pp. 434-439).
Janssen, J. & Corporaal, H. (1998). Registers on Demand; an integrated region scheduler and register allocator. Proc. of Conference on Compiler Construction, Lisbon, Portugal, April 1998.
Karkowski, I. & Corporaal, H. (1998). Design Space Exploration Algorithm For Heterogeneous Multi-processor Embedded System Design. Design and Automation Conference 35th (DAC) 15-19 June 1998. (pp. 82-87).
Karkowski, I. & Corporaal, H. (1998). Exploiting Fine- and Coarse-grain paralllelism in Embedded Programs. Proc. of the International Conference PACT'98, Paris, October 1998.
Leijten, J.A.J., Timmer, A.H., Meerbergen, J. van & Jess, J.A.G. (1998). Stream communication between real-time tasks in a high-performance multiprocessor. In A. Kunzmann (Ed.), Proc. Conference on Design, Automation and Test in Europe, DATE. (pp. 125-131). Los Alamitos, CA: IEEE Computer Society.
Nobrega Tavares, R. da & Berkelaar, M.R.C.M. (1998). Low power pass transistor networks. In J.P. Veen (Ed.), Proc. ProRISC/IEEE and STW's CSSP98/SAFE98. (pp. 541-544). Utrecht, Netherlands: IEEE European Chapter, Stichting Technische Wetenschappen.
Nobrega Tavares, R. da & Berkelaar, M.R.C.M. (1998). Reducing power consumption for PLAs. In J.P. Veen (Ed.), Proc. ProRISC/IEEE and STW's CSSP98/SAFE98. (pp. 535-539). Utrecht, Netherlands: IEEE European Chapter, Stichting Technische Wetenschappen.
Nobrega Tavares, R. da, Berkelaar, M.R.C.M. & Jess, J.A.G. (1998). Low power PLAs. Proc. International Workshop on Logic Synthesis. (pp. 366-374).
Rutten, J.W.J.M. & Berkelaar, M.R.C.M. (1998). Efficient exact and heuristic minimization of hazard-free logic. In Chin-Long Wey (Ed.), Proc. 1998 IEEE International Conference on Computer Design: VLSI in Computers and Processors. (pp. 152-159). Los Alamitos, CA: IEEE Computer Society.
Rutten, J.W.J.M. & Berkelaar, M.R.C.M. (1998). Multi-level synthesis for asynchronous logic. In J.P. Veen (Ed.), Proc. ProRISC/IEEE and STW's CSSP98/SAFE98. (pp. 467-471). Utrecht, Netherlands: IEEE European Chapter, Stichting Technische Wetenschappen.
Rutten, J.W.J.M. & Berkelaar, M.R.C.M. (1998). Towards multi-level synthesis for asynchronous logic. Proc. International Workshop on Logic Synthesis. (pp. 77-82).
Rutten, J.W.J.M., Berkelaar, M.R.C.M., Eijk, C.A.J. van & Kolsteren, M.A.J. (1998). An efficient divide and conquer algorithm for exact hazard free logic minimization. In A. Kunzmann (Ed.), Proc. Conference on Design, Automation and Test in Europe, DATE. (pp. 749-754). Los Alamitos, CA: IEEE Computer Society.
Schoenmakers, P.J. & Theeuwen, J.F.M. (1998). Clock gating on RT-level VHDL. Proc. International Workshop on Logic Synthesis. (pp. 387-391).
Villar dos Santo, L.C. (1998). Modeling speculative execution and availability analysis with Boolean expressions. In J.P. Veen (Ed.), Proc. ProRISC/IEEE and STW's CSSP98/SAFE98. (pp. 485-491). Utrecht, Netherlands: IEEE European Chapter, Stichting Technische Wetenschappen.

1997

Mesman, B., Strik, M.T.J., Timmer, A.H., Meerbergen, J. van & Jess, J.A.G. (1997). An integrated approach to register binding and scheduling. In J.P. Veen (Ed.), Proc. CSSP-97, 8th Annual ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing. (pp. 415-425). Utrecht, Netherlands: STW, Technology Foundation.
Mesman, B., Strik, M.T.J., Timmer, A.H., Meerbergen, J. van & Jess, J.A.G. (1997). Constraint analysis for DSP code generation. Proc. International Symposium on System Synthesis, ISSS'97. (pp. 33-40).
Mesman, B., Strik, M.T.J., Timmer, A.H., Meerbergen, J. van & Jess, J.A.G. (1997). Constraint driven loop pipelining. Proc. International Workshop on Logic and Architectural Synthesis, WLAS97. (pp. 205-211).
Berkelaar, M.R.C.M. (1997). Analyzing delay uncertainties: statistical delay calculation. In J.P. Veen (Ed.), Proc. CSSP-97, 8th Annual ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing. (pp. 415-425). Utrecht, Netherlands: STW, Technology Foundation.
Berkelaar, M.R.C.M. (1997). Statistical delay calculation, a linear time method. Proc. 1997 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems. (pp. 15-24).
Berkelaar, M.R.C.M. (1997). Statistical delay calculation. Workshop Notes 1997 ACM/IEEE International Workshop on Logic Synthesis, IWLS'97. (pp. 2.1.1-2.1.4).
Eijk, C.A.J. van & Jess, J.A.G. (1997). Towards the functional verification of large sequential circuits. Workshop Notes 1997 ACM/IEEE International Workshop on Logic Synthesis, IWLS'97. (pp. 1.1-1.4).
Eijk, C.A.J. van (1997). A BDD-based verification engine for combinational equivalence checking. In J.P. Veen (Ed.), Proc. CSSP-97, 8th Annual ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing. (pp. 155-162). Utrecht, Netherlands: STW, Technology Foundation.
Eijk, C.A.J. van (1997). Exploiting functional dependencies in sequential equivalence checking. In B. Becker, R. Bryant, M. Fujita & C. Meinel (Eds.), Proc. Computer Aided Design and Test-Decision Diagrams: Concepts and Applications. (pp. 14-15).
Jacobs, E.T.A.F. (1997). Speed-accuracy trade-off in gate sizing. In J.P. Veen (Ed.), Proc. CSSP-97, 8th Annual ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing. (pp. 231-238). Utrecht, Netherlands: STW, Technology Foundation.
Leijten, J.A.J., Meerbergen, J. van, Timmer, A.H. & Jess, J.A.G. (1997). Prophid: a data-driven multi-processor architecture for high-performance DSP. Proc. European Design and Test Conference, ED&TC. (pp. 611-612).
Leijten, J.A.J., Meerbergen, J. van, Timmer, A.H. & Jess, J.A.G. (1997). Prophid: a heterogeneous multi-processor architecture for multimedia. Proc. International Conference on Computer Design '97. (pp. 164-169).
Manganaro, G. & Pineda de Gyvez, J. (1997). Computation with nonlinear dynamical systems. In J.P. Veen (Ed.), Proc. CSSP-97, 8th Annual ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing. (pp. 391-399). Utrecht, Netherlands: STW, Technology Foundation.
Nijssen, R.X.T. & Eijk, C.A.J. van (1997). Regular layout generation of logically optimized datapaths. Proc. International Symposium on Physical Design. (pp. 42-47).
Rutten, J.W.J.M. & Berkelaar, M.R.C.M. (1997). Improved state assignment for burst mode finite state machines. Advanced research in asynchronous circuits and systems (ASYNC) : international symposium : proceedings, 3rd, April 7-10, 1997, Eindhoven, The Netherlands. (pp. 228-239). New York: IEEE Press.
Rutten, J.W.J.M. & Eijk, C.A.J. van (1997). Asynchronous counters for low power applications. In J.P. Veen (Ed.), Proc. CSSP-97, 8th Annual ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing. (pp. 513-518). Utrecht, Netherlands: STW, Technology Foundation.
Rutten, J.W.J.M. & Kolsteren, M.A.J. (1997). A divide and conquer strategy for hazard free 2-level logic synthesis. Workshop Notes 1997 ACM/IEEE International Workshop on Logic Synthesis, IWLS'97. (pp. P2.1-P2.4).
Schoenmakers, P.J. & Jess, J.A.G. (1997). Facilities for testing control software. Proc. HLDVT'97. (pp. 131-135).
Schoenmakers, P.J. & Jess, J.A.G. (1997). Testing software suffering from hardware. In J.P. Veen (Ed.), Proc. CSSP-97, 8th Annual ProRISC/IEEE Workshop on Circuits, Systems and Signal processing. (pp. 551-557). Utrecht, Netherlands: STW, Technology Foundation.
Verhaegh, W.F.J., Lippens, P.E.R., Aarts, E.H.L. & Meerbergen, J. van (1997). Multidimensional periodic scheduling : a solution approach. Proceedings European Design and Test Conference (ED&TC'97, Paris, Framce, March 17-20, 1997). (pp. 468-474).
Villar dos Santo, L.C. (1997). A method to control compensation code during global scheduling. In J.P. Veen (Ed.), Proc. CSSP-97, 8th Annual ProRisc/IEEE Workshop on Circuits, Systems and Signal Processing. (pp. 527-534). Utrecht, Netherlands: STW, Technology Foundation.

1996

Arts, H.M.A.M., Berkelaar, M.R.C.M. & Eijk, C.A.J. van (1996). Polarized observability don't cares. Proc. International Conference on Computer-Aided Design. (pp. 626-631).
Eijk, C.A.J. van & Jess, J.A.G. (1996). Exploiting functional dependences in finite state machine verification. Proc. European Design and Test Conference, ED&TC. (pp. 9-14).
Eijk, C.A.J. van (1996). Model reduction techniques for sequential verification. In J.P. Veen (Ed.), Proc. ProRISC/IEEE-Benelux Workshop on Circuits, Systems and Signal Processing. (pp. 119-124). Utrecht, Netherlands: STW, Technology Foundation.
Jacobs, E.T.A.F. (1996). Using gate sizing to reduce glitch power. In J.P. Veen (Ed.), Proc. ProRISC/IEEE-Benelux Workshop on Circuits, Systems and Signal Processing. (pp. 183-188). Utrecht, Netherlands: STW, Technology Foundation.
Moreira-Tamayo, O. & Pineda de Gyvez, J. (1996). Filtering and spectral processing of 1-D signals using cellular neural networks. Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, 1996, ISCAS '96, 'Connecting the World', 12-15 May 1996, Atlanta, Georgia. (Vol. 3, pp. 76-79). New York: IEEE.
Nijssen, R.X.T. & Jess, J.A.G. (1996). Two-dimensional datapath regularity extraction. Proc. 1996 ACM/SIGDA Physical Design Workshop. (pp. 111-117).
Nijssen, R.X.T. & Eijk, C.A.J. van (1996). Regular layout generation of logically optimized datapaths. In J.P. Veen (Ed.), Proc. ProRISC/IEEE-Benelux Workshop on Circuits, Systems and Signal Processing. (pp. 239-244). Utrecht, Netherlands: STW, Technology Foundation.
Rutten, J.W.J.M. (1996). Asynchronous burst mode finite state machines. In J.P. Veen (Ed.), Proc. ProRISC/IEEE-Benelux Workshop on Circuits, Systems and Signal Processing. (pp. 273-278). Utrecht, Netherlands: STW, Technology Foundation.
Theeuwen, J.F.M. & Seelen, H.A.M. (1996). Power reduction through clock gating by symbolic manipulation. Proc. International Workshop on Logic and Architectural Synthesis. (pp. 184-191).
Theeuwen, J.F.M. (1996). Power dissipation reduction by clock gating. In J.P. Veen (Ed.), Proc. ProRISC/IEEE-Benelux Workshop on Circuits, Systems and Signal Processing. (pp. 349). Utrecht, Netherlands: STW, Technology Foundation.
Verhaegh, W.F.J., Lippens, P.E.R., Aarts, E.H.L., Meerbergen, J. van & Werf, A. van der (1996). Multidimensional periodic scheduling: model and complexity. In L. Bougé, P. Fraigniaud, A. Mignotte & Y. Robert (Eds.), Euro-Par'96 Parallel Processing (Proceedings, Lyon, France, August 26-29, 1996), volume II. (Lecture Notes in Computer Science, Vol. 1124, pp. 226-235). Berlin: Springer.
Villar dos Santo, L.C., Eijndhoven, J.T.J. van & Jess, J.A.G. (1996). Combining code motion and scheduling. In J.P. Veen (Ed.), Proc. ProRISC/IEEE-Benelux Workshop on Circuits, Systems and Signal Processing. (pp. 279-284). Utrecht, Netherlands: STW, Technology Foundation.
Villar dos Santo, L.C., Heijligers, M.J.M., Eijk, C.A.J. van, Eijndhoven, J.T.J. van & Jess, J.A.G. (1996). A constructive method for exploiting code motion. Proc. IEEE/ACM Symposium on System Synthesis. (pp. 51-56).

1995

Goossens, K.G.W. (1995). Reasoning about VHDL using operational and observational semantics. In Paolo E. Camurati & Hans Eveking (Eds.), Correct hardware design and verification methods : Proceedings of the IFIP WG 10.5 Advanced Research Working Conference ; October 2 - 4, 1995, Frankfurt/Main, Germany. (Lecture Notes in Computer Science, Vol. 987, pp. 311-327). Berlin: Springer Verlag.
Bergamaschi, R.A., Brand, D., Stok, L. & Berkelaar, M.R.C.M. (1995). Efficient use of large don't cares in high-level and logic synthesis. Proc. 1995 ACM/IEEE International Conference on Computer-Aided Design. (pp. 272-278).
Berkelaar, M.R.C.M. & Ginneken, L.P.P.P. van (1995). Effcient orthonormality testing for synthesis with pass-transistor selectors. Proc. 1995 ACM/IEEE International Conference on Computer-Aided Design. (pp. 256-263).
Berkelaar, M.R.C.M. & Ginneken, L.P.P.P. van (1995). Efficient orthonormality testing for synthesis with pass-transistor selectors. Proc. 1995 ACM/IEEE International Workshop on Logic Synthesis. (pp. 1.1-1.10).
Di, C. & Jess, J.A.G. (1995). An improvement of a fast and accurate CMOS bridging fault simulator. Proc. 6th International Symposium on IC Technology, Systems and Applications. (pp. 506-509).
Eijk, C.A.J. van & Jess, J.A.G. (1995). Detection of equivalent state variables in finite state machine verification. Proc. 1995 ACM/IEEE International Workshop on Logic Synthesis. (pp. 3.35-3.44).
Eijk, C.A.J. van & Janssen, G.L.J.M. (1995). Exploiting structural similarities in a BDD-based verification method. In T. Kropf & R. Kumar (Eds.), Proc. 2nd International Conference on Theorem Provers in Circuit Design, TPCD. (pp. 110-125). Springer Verlag.
Eijk, C.A.J. van (1995). Formal verification of sequential circuits using binary decision diagrams. In J.P. Veen (Ed.), Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing. (pp. 75-82). Utrecht, Netherlands: STW, Technology Foundation.
Fleurkens, J.W.G., Eijk, C.A.J. van & Jess, J.A.G. (1995). Run-time consistency checking in discrete simulation models. Proc. European Design and Test Conference, ED&TC. (pp. 223-227).
Heijligers, M.J.M. & Jess, J.A.G. (1995). High-level synthesis scheduling and allocation using genetic algorithms based on construction topology scheduling techniques. Proc. International Conference on Evolutionary Computation. (pp. 56-61).
Heijligers, M.J.M., Cluitmans, L.J.M. & Jess, J.A.G. (1995). High-level synthesis scheduling and allocation using genetic algorithms. Proc. Asia and South Pacific Design Automation Conference. (pp. 61-66).
Hurk, J.A.A.M. van den & Dilling, E.R. (1995). System level design, a VHDL based approach. Proc. European Design Automation Conference, EuroDAC. (pp. 568-573).
Hurk, J.A.A.M. van den & Frencken, P.H. (1995). A concept for source decoding in digital video broadcast applications. Proc. International Conference on Consumer Electronics, ICCE. (pp. 260-261).
Hurk, J.A.A.M. van den & Schutte, R. (1995). Prototyping for MPEG2 with programmable logic devices. In J.P. Veen (Ed.), Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing. (pp. 145-152). Utrecht, Netherlands: STW, Technology Foundation.
Janssen, G.L.J.M. (1995). Application of BDD's in formal verification. Proc. 22nd International School and Conference on CAD. (pp. 49-53).
Leijten, J.A.J., Meerbergen, J. van & Jess, J.A.G. (1995). Analysis and reduction of glitches in synchronous networks. Proc. European Design and Test Conference, ED&TC. (pp. 398-403).
Strik, M.T.J., Meerbergen, J. van, Timmer, A.H., Jess, J.A.G. & Note, S. (1995). Efficient code generation for in-house DSP-cores. Proc. European Design and Test Conference, ED&TC. (pp. 244-249).
Timmer, A.H. & Jess, J.A.G. (1995). Exact scheduling strategies based on bipartite graph matching. Proc. European Design and Test Conference, ED&TC. (pp. 42-47).
Timmer, A.H., Strik, M.T.J., Meerbergen, J. van & Jess, J.A.G. (1995). Conflict modelling and instruction scheduling in code generation for in-house DSP cores. Proc. 32nd Design Automation Conference, DAC. (pp. 593-598).
Villar dos Santo, L.C., Wagner, T.V. & Geutz, G. (1995). Digimodem: an ASIC for a familiy of high-speed modems. Proc. European Design and Test Conference, ED&TC. (pp. 87-90).

1994

Berkelaar, M.R.C.M., Buurman, H.W. & Jess, J.A.G. (1994). Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. Proc. 1994 IEEE/ACM International Conference on Computer-Aided Design. (pp. 474-480).
Eijk, C.A.J. van & Janssen, G.L.J.M. (1994). Exploiting structural similarities in a BDD-based verification method. Proc. 2nd Conference on Theorem Provers in Circuit Design. (pp. 151-166).
Eijk, C.A.J. van (1994). Formal verification of combinational circuits using binary decision diagrams. Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing. (pp. 97-100).
Eijndhoven, J.T.J. van (1994). CMOS cell generation for logic synthesis. In Wang Yangyan (Ed.), Proc. 1st International Conference on ASIC, ASICON 94. (pp. 75-78). Beijing, China: Electr. Ind. Publ. House.
Heijligers, M.J.M., Hilderink, H.A. & Timmer, A.H. (1994). NEAT: an object-oriented high-level synthesis interface. Proc. IEEE International Symposium on Circuits and Systems. (pp. 1233-1236).
Hilderink, H.A. (1994). NESCIO: an interactive high level synthesis framework. Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing. (pp. 119-124).
Huijbregts, E.P., Eijndhoven, J.T.J. van & Jess, J.A.G. (1994). On design rule correct maze routing. Proc. European Design and Test Conference, ED&TC. (pp. 407-411).
Nijssen, R.X.T. & Jess, J.A.G. (1994). Datapath regularity extraction. Proc. IFIP Workshop on Logic and Architecture Synthesis. (pp. 205-218).
Timmer, A.H. (1994). Improved execution interval and binding analysis. Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal Processing. (pp. 247-251).
Werf, A. van der, Aarts, E.H.L., Heijnen, E.W., Meerbergen, J. van, Verhaegh, W.F.J. & Lippens, P.E.R. (1994). A new method for retiming multi-functional processing units. In K. Yanagawa & P.A. Ivey (Eds.), VLSI'93 (Proceedings of the IFIP TC 10/WG 10.5 International Conference on Very Large Scale Integration, Grenoble, France, September 7-10, 1993). (IFIP Transactions A : Computer science and technology, Vol. A-42, pp. 191-200). Amsterdam: North-Holland.
Werf, A. van der, Meerbergen, J. van, Aarts, E.H.L., Verhaegh, W.F.J. & Lippens, P.E.R. (1994). Efficient timing constraint derivation for optimally retiming high speed processing units. Proceedings 7th International Symposium on High-Level Synthesis (Niagara-on-the-Lake ON, Canada, May 18-20, 1994). (pp. 48-53). IEEE.
Xue, H., Di, C. & Jess, J.A.G. (1994). Probability analysis for CMOS floating gate faults. Proc. European Design and Test Conference, ED&TC. (pp. 443-449).
Xue, H., Huijbregts, E.P. & Jess, J.A.G. (1994). Routing for manufacturability. Proc. 31st ACM/IEEE Design Automation Conference. (pp. 402-406).
Yin, J., Pineda de Gyvez, J. & Lu, M. (1994). An automatic system for measuring electromagnetic parameters for oil field pipes. Proceedings Industrial Technology, 1994. Proceedings of the IEEE International Conference, Guangzhou , China , 5-9 Dec 1994. (pp. 784-788). Piscatawau: IEEE.

1993

Goossens, K.G.W. (1993). Structure and behaviour in hardware verification. In J.J. Joyce & C.J.H. Seger (Eds.), Higher order logic theorem proving and its applications : proceedings of the 6th international workshop, HUG '93, August 11 - 13, 1993, Vancouver, B.C., Canada. (Lecture Notes in Computer Science, Vol. 780, pp. 75-88). London, UK: Springer Verlag.
Goossens, K.G.W. (1993). The Formalisation of a hardware description language in a proof system: motivation and applications. Proceedings of the XIII Conference of the Brazilian Computer Society. Florianopolis, Brazil.

1992

Goossens, K.G.W. (1992). Operational semantics based formal symbolic simulation. In L. Claesen & M. Gordon (Eds.), Higher order logic theorem proving and its applications : proceedings of the IFIP TC10/WG10.2 International Workshop on Higher Order Logic Theorem Proving and Its Applications - HOL '92, 21-24 September 1992, Leuven, Belgium. (IFIP Transactions A : Computer science and technology, Vol. 20, pp. 487-506). Amsterdam: North-Holland / Elsevier.
Cramers, C.A.M.G., Schoenmakers, P.J. & Janssen, J.G.M. (1992). The position of supercritical-fluid chromatography between gas- and liquid chromatography from a kinetic point of view. In F. Dondi & G. Guiochon (Eds.), Theoretical advancement in chromatography and related separation techniques. (NATO ASI Series, Series C: Mathematical and Physical Sciences, Vol. 383, pp. 289-314). Dordrecht: Kluwer.
Verhaegh, W.F.J., Lippens, P.E.R., Aarts, E.H.L., Korst, J.H.M., Werf, A. van der & Meerbergen, J. van (1992). Efficiency improvements for force-directed scheduling. Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'92, Santa Clara CA, USA, November 8-12, 1992). (pp. 286-291).
Werf, A. van der, Peek, M.J.H., Aarts, E.H.L., Meerbergen, J. van, Lippens, P.E.R. & Verhaegh, W.F.J. (1992). Area optimization of multi-functional processing units. Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'92, Santa Clara CA, USA, November 8-12, 1992). (pp. 292-299).

1991

Jess, J.A.G., Pineda de Gyvez, J. & Di, C. (1991). Defect measuring, defect modeling, and inductive fault analysis. Proceedings of the VI SBMICRO Congress, July, 1991.
Goossens, K.G.W. (1991). Embedding a CHDDL in a proof system. In P. Prinetto & P. Camurati (Eds.), Advanced Research Workshop on Correct Hardware Design Methodologies. (pp. 359-374). North Holland.
Di, C. & Pineda de Gyvez, J. (1991). The analysis of spot defect induced faults in MOS circuits. Proceedings of the 1991 International Conference on Circuits and Systems, 16-17 June 1991, Shenzhen, China. (pp. 478-481). New York: IEEE.

1990

Pineda de Gyvez, J. & Jess, J.A.G. (1990). IC spot-defect and fault semantics - a unified framework. Proceedings of the IEEE International Symposium on Circuits and Systems, 1990, 1-3 May 1990, New Orleans, Louisiana. (Vol. 4, pp. 2712-2715). New York: IEEE.
Pineda de Gyvez, J. & Jess, J.A.G. (1990). Layout verification for fault and yield analysis. Proceedings of the 2nd Symposium on Design Methodology(PRORISC), April, 1990. (pp. 89-98).
Di, C. & Pineda de Gyvez, J. (1990). A spot-defect to fault collapsing technique. Proceedings of the 33rd Midwest Symposium on Circuits and Systems, 1990, 12-14 August 1990, Calgary, Altamont. (pp. 580-583). Piscataway: IEEE.

1989

Pineda de Gyvez, J. & Jess, J.A.G. (1989). A layout defect-sensitivity extractor. Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989, ICCAD-89, 5-9 November 1989, Santa Clara, California. (pp. 538-541). New York: IEEE.
Pineda de Gyvez, J. & Jess, J.A.G. (1989). On the definition of critical areas for IC photolithographic spot defects. Proceedings of the 1st European Test Conference, 1989, 12-14 April 1989, Paris, France. (pp. 152-158). New York: IEEE.

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Report

2011

Jordans, R., Solon Nery, A., Corvino, R. & Jozwiak, L. (2011). Report on the optimal instruction hardware implementation. ARTEMIS No. 2009-1-ASAM-100265-D4.4, Eindhoven: ASAM, 58 pp.
Jordans, R., Corvino, R., Diken, E., Jozwiak, L., Lindwer, M., Cocco, M., Shah, S.A.A. & Berekovic, M. (2011). Method of final ASIP architecture construction. ARTEMIS No. 2009-1-ASAM-100265-D3.3, Eindhoven: ASAM, 44 pp.
Nugteren, C. & Corporaal, H. (2011). A modular and parameterisable algorithm classification. ES Reports No. ESR-2011-02, Eindhoven: Eindhoven University of Technology.
Diken, E., Jordans, R., Corvino, R. & Jozwiak, L. (2011). Method of and report on application analysis/profiling and parallelization. ARTEMIS No. 2009-1-ASAM-100265-D3.1, Eindhoven: ASAM, 98 pp.
Diken, E., Corvino, R. & Jozwiak, L. (2011). Prototype tools for application analysis/profiling and parallelization. ARTEMIS No. 2009-1-ASAM-100265-D3.5, Eindhoven: ASAM, 44 pp.
Corvino, R., Jordans, R., Diken, E. & Jozwiak, L. (2011). Instruction set synthesis. ARTEMIS No. 2009-1-ASAM-100265-D3.2, Eindhoven: ASAM, 52 pp.
Lindwer, M., Cocco, M., Corvino, R., Jordans, R., Jozwiak, L., Madsen, J., Meloni, P., Raffo, L., Notarangelo, G. & Kienhuis, B. (2011). Final design methodology, flow, and tool requirements. ARTEMIS No. 2009-1-ASAM-100265- D1.2, Eindhoven: ASAM, 60 pp.
Micconi, L., Madsen, J., Pop, P., Kienhuis, B., Corvino, R. & Jozwiak, L. (2011). Report on initial version of the hierarchical application model. ARTEMIS No. 2009-1-ASAM-100265-D2.2, Eindhoven: ASAM, 21 pp.

2010

Trcka, N., Voorhoeve, M. & Basten, A.A. (2010). Parameterized timed partial orders with resources: formal definition and semantics. ES Reports No. ESR-2010-01, Eindhoven: Technische Universiteit Eindhoven, 10 pp.
Siyoum, F.M., Akesson, K.B. & Stuijk, S. (2010). Dataflow model for credit-controlled static-priority arbitration. ES Reports No. ESR-2010-3, Eindhoven: Technische Universiteit Eindhoven, 22 pp.
Poplavko, P., Geilen, M.C.W. & Basten, A.A. (2010). Predicting the throughput of multiprocessor applications under dynamic workload. ES Reports No. ESR-2010-02, Eindhoven: Technische Universiteit Eindhoven, 10 pp.

2008

Funk, M., Putten, P.H.A. van der & Corporaal, H. (2008). UML profile for modeling system observation. ES Reports No. ESR-2008-09, Eindhoven: Technische Universiteit Eindhoven, 13 pp.
Funk, M., Rozinat, A., Alves De Medeiros, A.K., Putten, P.H.A. van der, Corporaal, H. & Aalst, W.M.P. van der (2008). Semantic concepts in product usage monitoring and analysis. ES Reports No. ESR-2008-10, Eindhoven: Technische Universiteit Eindhoven, 20 pp.
Hartel, P.H., Ruys, T.C. & Geilen, M.C.W. (2008). Scheduling Optimisations for SPIN to Minimise Buffer Requirements in Synchronous Data Flow (with Appendix). Techincal Report No. CTIT-08-16, Enschede: Universiteit Twente.
Kumar, A., Mesman, B. & Corporaal, H. (2008). Accurate run-time performance prediction for multi-application multiprocessor systems. ES Reports No. ESR-2008-07, Eindhoven: Technische Universiteit Eindhoven, 18 pp.
Stanley-Marbell, P. & Marculescu, D. (2008). Deviation-tolerant computation in concurrent failure-prone hardware. ES Reports No. ESR-2008-01, Eindhoven: Technische Universiteit Eindhoven, 22 pp.
Stanley-Marbell, P. (2008). Ladon : a 24-processor low-power performance-scalable processor module for sensor platforms. ES Reports No. ESR-2008-05, Eindhoven: Technische Universiteit Eindhoven, 14 pp.
Stanley-Marbell, P. (2008). A mobile client platform for sensor networks. ES Reports No. ESR-2008-04, Eindhoven: Technische Universiteit Eindhoven, 15 pp.
Stanley-Marbell, P. (2008). A programming model and language implementation for error-tolerant networks of computation. ES Reports No. ESR-2008-03, Eindhoven: Technische Universiteit Eindhoven, 12 pp.
Stanley-Marbell, P. (2008). Encoding efficiency bounds for digital number representations under value deviation constraints. ES Reports No. ESR-2008-02, Eindhoven: Technische Universiteit Eindhoven, 8 pp.
Stanley-Marbell, P., Basten, A.A., Rousselot, J., Serna Oliver, R., Karl, H., Geilen, M.C.W., Hoes, R.J.H., Fohler, G. & Decotignie, J.D. (2008). System models in wireless sensor networks. ES Reports No. ESR-2008-06, Eindhoven: Technische Universiteit Eindhoven, 18 pp.
Theelen, B.D., Geilen, M.C.W., Stuijk, S., Gheorghita, Valentin, Basten, A.A., Voeten, J.P.M. & Ghamarian, A.H. (2008). Scenario-aware dataflow. ES Reports No. ESR-2008-08, Eindhoven: Technische Universiteit Eindhoven, 22 pp.

2007

Kumar, Akash, Mesman, B., Corporaal, H., Theelen, B.D. & Ha, Y. (2007). A probabilistic approach to model resource contention for performance estimation of multi-features media devices. ES Reports No. ESR-2007-02, Eindhoven: Technische Universiteit Eindhoven.
Pineda de Gyvez, J., Breems, L.J. & Lenaerts, D. (2007). Visit report ISLPED 2007. NXP-R-TN 2007 No. 00223, Eindhoven: Philips Research.
Brand, J.W. van den, Bekooij, M.J.G., Moonen, A.J.M. & Moonen, A.J.M. (2007). Streaming memory consistency for efficient MPSoC design. ES Reports No. ESR-2007-03, Eindhoven: Technische Universiteit Eindhoven, 10 pp.
Ghamarian, A.H., Geilen, M.C.W., Basten, A.A. & Stuijk, S. (2007). Parametric throughput analysis of synchronous data flow graphs. ES Reports No. ESR-2007-08, Eindhoven: Technische Universiteit Eindhoven.
Ghamarian, A.H., Stuijk, S., Basten, A.A., Geilen, M.C.W. & Theelen, B.D. (2007). Latency minimization for synchronous data flow graphs. ES Reports No. ESR-2007-04, Eindhoven: Technische Universiteit Eindhoven.
Gheorghita, Valentin, Palkovic, M., Hamers, J., Vandecapelle, A., Mamagkakis, S., Basten, A.A., Eeckhout, L., Corporaal, H., Catthoor, F., Vandeputte, F. & Bosschere, K. De (2007). System scenario based design of dynamic embedded systems. ES Reports No. ESR-2007-06, Eindhoven: Technische Universiteit Eindhoven, 46 pp.
Meijer, M. & Pineda de Gyvez, J. (2007). Voltage, frequency and body bias control for power performance tuning. NXP-R-TN-2007 No. 00273, Eindhoven: Philips Research.
Moonen, A.J.M., Moonen, A.J.M., Bekooij, M.J.G., Berg, R.M. van den & Meerbergen, J. van (2007). Evaluation of the throughput computed with a dataflow model : a case study. ES Reports No. ESR-2007-01, Eindhoven: Technische Universiteit Eindhoven, 9 pp.
Moonen, A.J.M., Moonen, A.J.M., Bekooij, M.J.G., Berg, R.M.J. van den & Meerbergen, J. van (2007). Analysing the impact of a communication assist in a multiprocessor system-on-chip. ES Reports No. ESR-2007-05, Eindhoven: Technische Universiteit Eindhoven, 8 pp.
Stanley-Marbell, P. (2007). Current measurement daughtercard for Logicpd i.MX31 LITEKIT evaluation board. ES Reports No. ESR-2007-07, Eindhoven: Technische Universiteit Eindhoven, 5 pp.

2006

Geilen, M.C.W., Seneclauze, M., Blanch, C., Fohler, G., Isovic, D. & Stok, P.D.V. van der (2006). Deliverable D2f, Stream description methods. IST No. IST 2004-004042, Eindhoven: TU Eindhoven, 61 pp.
Stuijk, S., Geilen, M.C.W. & Basten, A.A. (2006). Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs. ES Reports No. ESR-2006-01, Eindhoven: Technische Universiteit Eindhoven, 11 pp.
Florescu, O., Voeten, J.P.M. & Corporaal, H. (2006). Modelling patterns for analysis and design of real-time systems. ES Reports No. ESR-2006-5, Eindhoven: Technische Universiteit Eindhoven, 25 pp.
Florescu, O., Huang, J., Voeten, J.P.M. & Corporaal, H. (2006). Towards stronger property preservation in real-time System synthesis. ES Reports No. ESR-2006-02, Eindhoven: Technische Universiteit Eindhoven, 21 pp.
Ghamarian, A.H., Geilen, M.C.W., Basten, A.A., Theelen, B.D., Mousavi, M.R. & Stuijk, S. (2006). Liveness and boundedness of synchronous data flow graphs. ES Reports No. ESR-2006-04, Eindhoven: Technische Universiteit Eindhoven, 14 pp.
Gheorghita, Valentin, Basten, A.A. & Corporaal, H. (2006). An overview of application scenario usage in streaming-oriented embedded system design. ES Reports No. ESR-2006-03, Eindhoven: Technische Universiteit Eindhoven, 20 pp.
Zjajo, A. & Pineda de Gyvez, J. (2006). Analog automatic test pattern generation. Technical Note No. NL-2005/00912, Eindhoven: Philips Research Labs.

2005

Geilen, M.C.W., Basten, A.A. & Stuijk, S. (2005). Minimising buffer requirements of synchronous dataflow graphs with model checking. ES Reports No. ESR-2005-01, Eindhoven: Technische Universiteit Eindhoven, 11 pp.
Geilen, M.C.W., Basten, A.A., Theelen, B.D. & Otten, R.H.J.M. (2005). An algebra of Pareto points. ES Reports No. ESR-2005-02, Eindhoven: Technische Universiteit Eindhoven, 17 pp.
Geilen, M.C.W., Joosten, M., Decotignie, J.D., Sénéclauze, M., Blanch, C., Koulamas, C., Papadopoulos, G., Prayati, A., Fohler, G., Isovic, D., Doren, G. van, Groot, E.H. de, Heesch, D., Otero Perez, C., Stok, P.D.V. van der, Basten, A.A. & Theelen, B.D. (2005). Description of high-level architecture and definition of components and functional entities. Deliverable D1b. IST-004042-BETSY, Eindhoven: Philips Research Laboratories, 79 pp.
Stuijk, S. & Basten, A.A. (2005). Analyzing concurrency in streaming applications. ES Reports No. ESR-2005-05, Eindhoven: Technische Universiteit Eindhoven, 27 pp.
Stuijk, S., Geilen, M.C.W. & Basten, A.A. (2005). Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs. ES Reports No. ESR-2005-07, Eindhoven: Technische Universiteit Eindhoven, 14 pp.
Stuijk, S., Ghamarian, A.H., Basten, A.A., Geilen, M.C.W. & Theelen, B.D. (2005). Time-constrained energy-aware routing and scheduling of network-on-chip communication. ES Reports No. ESR-2005-08, Eindhoven: Technische Universiteit Eindhoven, 13 pp.
Florescu, O., Voeten, J.P.M. & Corporaal, H. (2005). Predicting implementation accuracy for real-time control systems. ES Reports No. ESR-2005-09, Eindhoven: Technische Universiteit Eindhoven, 18 pp.
Gheorghita, Valentin, Stuijk, S., Basten, A.A. & Corporaal, H. (2005). Sharper WCET upper bounds using automatically detected scenarios. ES Reports No. ESR-2005-04, Eindhoven: Technische Universiteit Eindhoven, 13 pp.
Isovic, D., Fohler, G., Prayati, A., Koulamas, C., Papadopoulos, G., Decotignie, J.D., Sénéclauze, M., Joosten, M., Bernhardi, R., Geilen, M.C.W., Theelen, B.D., Basten, A.A., Perez, C.O., Steffens, E.F.M., Stok, P.D.V. van der, Blanch, C. & Denolf, K. (2005). Report on temporal impact of identified entities on end-to-end-timing. BETSY No. IST-2004-004042, Eindhoven: Philips Research Labs., 49 pp.
Poplavko, P., Pastrnak, M., Basten, A.A., Meerbergen, J. van, Bekooij, M.J.G. & With, P.H.N. de (2005). Run-time prediction of execution times of stream-oriented applications in multiprocessors on chip. ES Reports No. ESR-2005-06, Eindhoven: Technische Universiteit Eindhoven, 17 pp.
Westra, H.J.L. & Groeneveld, P.R. (2005). Towards integration of quadratic placement and pin assignment. ES Reports No. ESR-2005-03, Eindhoven: Technische Universiteit Eindhoven, 8 pp.

2004

Geilen, M.C.W., Basten, A.A., Mesman, B., Poplavko, P., Zhao, Q. & Charot, F. (2004). Development Support Implementation Report. Deliverable D13c No. 2000-30026, Eindhoven, the Netherlands: Philips Research Labs, 74 pp.
Basten, A.A. (2004). Ozone Platform Architecture Implementation Report. Deliverable D13 No. 2000-30026, Eindhoven, the Netherlands: Philips Research Labs, 16 pp.
Meijer, M. & Pineda de Gyvez, J. (2004). Adaptive voltage scaling circuit implementations and islands of voltage for system-on-chip applications, Philips Research Technical Note No. 00239, Eindhoven: Philips Research.

2003

Basten, A.A., Geilen, M.C.W., Mesman, B., Zhao, Q., Lafruit, G., Brinker, A.C. den, Groot, H. de, Hentschel, C., Kastrup, B., Papalau, L., Steffens, E.F.M., Wolf, P. v d, Francois, E., Guillotel, Ph., Ruellou, P., Benatallah, S. & Charot, F. (2003). Intermediate Ozone Platform Architecture Implementation Report. Deliverable D8c, Eindhoven, the Netherlands: Philips Research Labs, 35 pp.
Mousavi, M.R., Guernic, P. le, Talpin, J.-P., Shukla, S.K. & Basten, A.A. (2003). Modeling and Validation of Globally Asynchronous Design in Synchronous Frameworks. No. RR-4935, Rennes, France: INRIA, 18 pp.
Pineda de Gyvez, J. & Rius, J. (2003). Built-in current sensor for delta-iddq testing, Natlab Technical Note No. 0187, Eindhoven: Philips Research.
Pineda de Gyvez, J., Domans, W. & Wagemans, A.G. (2003). RF and Mixed Signal Testing in the Sector IC Design of Philips Research, Natlab Technical Note No. 0150, Eindhoven: Philips Research.
Pineda de Gyvez, J., Gronthoud, G. & Amine, R. (2003). VDD ramp testing for RF circuits, Philips Research Technical Note No. 00864, Eindhoven: Philips Research.
Arumi, D., Pineda de Gyvez, J. & Gronthoud, G. (2003). ATPG for parametric and weak delay faults, Natlab Technical Note No. 00409, Eindhoven: Philips Research.
Cerisara, C., Issarny, V., Laprie, Y. & Basten, A.A. (2003). Ozone Intermediate Status Report on the Implementation. Deliverable D8. No. 2000-30026, Eindhoven: Philips Research Laboratories, 10 pp.
Pavlov|, ., Sachdev, M. & Pineda de Gyvez, J. (2003). Investigation of design for testability issues in embedded SRAMS, Natlab Technical Note No. 00073, Eindhoven: Philips Research.

2002

Verbeek, H.M.W. & Basten, A.A. (2002). Deciding life-cycle inheritance on Petri nets. BETA publicatie : working papers No. 85, Eindhoven: Technische Universiteit Eindhoven, 20 pp.
Basten, A.A., Geilen, M.C.W., Lafruit, G., Groot, H. de, Papalau, L.M., Steffens, E.F.M. & Guillotel, Ph. (2002). Ozone Platform Architecture Design. Deliverable D6, Eindhoven: Philips Research Labs, 20 pp.
Mousavi, M.R., Basten, A.A., Reniers, M.A., Chaudron, M.R.V. & Russello, G. (2002). Separating functionality, behaviour and timing in the design of reactive systems: (GAMMA+Coordination)+Time. Computer Science Report No. 02-09, Eindhoven: Technische Universiteit Eindhoven, 95 pp.
Mousavi, M.R., Russello, G., Chaudron, M.R.V., Reniers, M.A., Basten, A.A., Corsaro, A., Shukla, S.K., Gupta, R.K. & Schmidt, D.C. (2002). Aspects + GAMMA = AspectGAMMA : A formal framework for aspect-oriented specification. Technical Report No. CECS-02-01, Irvine CA, USA: Center for Embedded Computer Systems, UCI, 13 pp.
Pineda de Gyvez, J. & Tuinhout, H. (2002). Intra-die leakage current behavior of digital CMOS circuits: a threshold voltage mismatch perspective, NatLab Technical Note No. 058, Eindhoven: Philips Research.
Pessolano, F., Petrescu, V., van Deursen, T., Rao, K., Garg, M., van der Weide, G., Dielissen, J., Sevat, L., Wielage, P., Theunissen, B., van Dijk, S., Pineda de Gyvez, J. & Goosens, M. (2002). NatLab Technical Note. NatLab Technical Note No. 145, Eindhoven: Philips Research.
Simons, D., Groot, H. de, Issamy, V., Cerisera, Ch., Laprie, Y., Guillotel, Ph., Kerdranvat, M., Basten, A.A. & Geilen, M.C.W. (2002). Ozone Risk Management Plan. Deliverable D2c, Eindhoven: Philips Research Labs., 27 pp.
Simons, D., Groot, H. de, Issamy, V., Cerisera, Ch., Laprie, Y., Guillotel, Ph., Kerdranvat, M., Basten, A.A. & Geilen, M.C.W. (2002). Ozone Specification. Deliverable D2, Eindhoven: Philips Research Lab., 162 pp.
Zhao, Q., Mesman, B. & Basten, A.A. (2002). Static Resource Models for Code-Size Efficient Embedded Processors. EUT report No. 02-E-312, onbekend: Electronic Systems, 30 pp.

2001

Pineda de Gyvez, J. & Wetering, E. van der (2001). Leakage behavior in deep submicron logic CMOS logic circuits: modelling and estimation, Nat. Lab. Rep 7166, Eindhoven: Philips Research.
Bos, G., Mels, A., Volf, P., van de Pol, M., Slenter, A., Simon, P., Pineda de Gyvez, J., Trivedi, N., Nguyen, J., Nguyen, D. & Korenhof, M. (2001). Veqtor12 test spec: vehicle for development, qualification and monitoring of the CMOS12 process, veqtor12 E-sort test specification, Philips Semiconductors PE No. DFM M4Y TC-Microtel, Eindhoven: Philips Research.
Slenter|, ., Pol, M. van de, Volf, P., Mels, A., Simon, P., Pineda de Gyvez, J., Trivedi, N., Nguyen, J., Nguyen, D., Korenhof, M. & Bos, G. (2001). Veqtor12 spec: vehicle for development, qualification and monitoring of the CMOS12 process, veqtor12 specification, Philips Semiconductors PE No. DFM M4Y TC-Microtel, Eindhoven: Philips Research.

2000

Aalst, W.M.P. van der & Basten, A.A. (2000). Inheritance of workflows: an approach to tackling problems related to change. BETA report No. WP 50, onbekend: Faculteit Wiskunde en Informatica, 68 pp.
Verbeek, H.M.W., Basten, A.A. & Aalst, W.M.P. van der (2000). Diagnosing workflow processes using Woflan. BETA Report No. WP 48, onbekend: Faculteit Wiskunde en Informatica, 40 pp.

1999

Aalst, W.M.P. van der & Basten, A.A. (1999). Inheritance of workflows : an approach to tackling problems related to change. Computing Science Reports No. 99-06, Eindhoven: Technische Universiteit Eindhoven, 66 pp.
Baeten, J.C.M. & Basten, A.A. (1999). Partial-order process algebra (and its relation to Petri nets). Computing Science Reports No. 99-18, Eindhoven: Technische Universiteit Eindhoven, 79 pp.
Verbeek, H.M.W., Basten, A.A. & Aalst, W.M.P. van der (1999). Diagnosing workflow processes using Woflan. Computing Science Reports No. 99-02, Eindhoven: Technische Universiteit Eindhoven, 44 pp.
Basten, A.A. & Aalst, W.M.P. van der (1999). Inheritance of behavior. Computing Science Reports No. 99-17, Eindhoven: Technische Universiteit Eindhoven, 83 pp.

1998

Basten, A.A. & Hooman, J.J.M. (1998). Process algebra in PVS. Computing Science Reports No. 98-10, Eindhoven: Technische Universiteit Eindhoven, 17 pp.
Pineda de Gyvez, J., Sanchez-Sinencio, E., Han, G. & Gonzalez, O. (1998). A VLSI acceleration for high speed simulation of oil reservoir, mid-term project report. Contract C97-00372, Eindhoven: Philips Research.
Alba Pinto, C.A. & Eijndhoven, J.T.J. van (1998). The HDVO scheduler., 16 pp.
Dalen, E.J. van (1998). A new framework for a digital media broadcasting stream processor., 55 pp.
Eijndhoven, J.T.J. van & Bloks, R.H.J. (1998). TM-Prommpt CPU64 exception handling., 28 pp.
Sijstermans, F.W., Eijndhoven, J.T.J. van, Pol, E.J., Rathnam, S. & Slavenburg, G.A. (1998). TM-Prommpt 64-bit CPU., 260 pp.

1997

Eijndhoven, J.T.J. van (1997). TMPrompt 16-bit compliant software IDCT., 36 pp.
Houtert, J.G.M. (1997). Design of a multi-stream processor., 50 pp.
Kloprogge, R.J.L. (1997). Development and application of a general-purpose stream processor for an MPEG systems decoder., 60 pp.
Lammers, K.J. (1997). Design flow and communication., 70 pp.
Siepe, A.H.M., Rietkerken, B.A.M. & Thomasse, B.F.A. (1997). New outlooks for TV: the process of creating new products to boost TV functionality., onbekend: Electronic Systems, 50 pp.

1996

Aalst, W.M.P. van der & Basten, A.A. (1996). Life-cycle inheritance : a Petri-net-based approach. Computing Science Reports No. 96-06, Eindhoven: Technische Universiteit Eindhoven, 18 pp.
Basten, A.A. & Aalst, W.M.P. van der (1996). A process-algebraic approach to life-cycle inheritance : inheritance = encapsulation + abstraction. Computing Science Reports No. 96-05, Eindhoven: Technische Universiteit Eindhoven, 15 pp.
Pineda de Gyvez, J. (1996). High performance image processing using cellular neural networks. TEES Final Research Report, Eindhoven: Philips Research.
Rietkerken, B.A.M. & Thomasse, B.F.A. (1996). New outlooks for TV: the process of creating new products to boost TV functionality., 50 pp.
Thomasse, B.F.A. & Rietkerken, B.A.M. (1996). New outlooks for TV: the process of creating new products to boost TV functionality., 50 pp.

1995

Basten, A.A. & Voorhoeve, M. (1995). An algebraic semantics for hierarchical P/T nets. Computing Science Reports No. 95-35, Eindhoven: Technische Universiteit Eindhoven, 32 pp.
Pineda de Gyvez, J. (1995). CNN VLSI implementation. TEES Progress Research Report 93-549 No. #5, Eindhoven: Philips Research.
Pineda de Gyvez, J. (1995). Feasibility study of a time-multiplexing approach using a 4x4 CNN laboratory Prototype, TEES Progress Research Report 93-549 No. #6, Eindhoven: Philips Research.
Pineda de Gyvez, J. (1995). Robust testing of cellular neural networks. TEES Progress Research Report 93-549 No. #4, Eindhoven: Philips Research.
Pineda de Gyvez, J. (1995). Time Multiplexed Color Image Processing Based on a VLSI Cellular Neural Network with Cell-State Outputs. TEES Progress Research Report, Eindhoven: Philips Research.
Gruijters, P.W.F. (1995). Architecture study for a DAB channel decoder., 80 pp.
Rensink, A.M. (1995). An integrated design flow for television applications., 50 pp.
Takken, R.M.H. (1995). Controller design for a single-chip MPEG-2 encoder., 75 pp.

1994

Basten, A.A., Bol, R.N. & Voorhoeve, M. (1994). Simulating and analyzing railway interlockings in ExSpect. Computing Science Reports No. 94-37, Eindhoven: Technische Universiteit Eindhoven, 30 pp.
Basten, A.A., Kunz, T.H., Black, J. & Taylor, D. (1994). Time and order of abstract events in distributed computations. Computing Science Notes No. 9406, Eindhoven: Technische Universiteit Eindhoven, 29 pp.
Pineda de Gyvez, J. (1994). Behavioral testing of cellular neural networks. TEES Progress Research Report 93-549 No. #3, Eindhoven: Philips Research.
Pineda de Gyvez, J. (1994). Cellular neural networks behavioral simulation. TEES Progress Research Report 93-549 No. #1, Eindhoven: Philips Research.
Pineda de Gyvez, J. (1994). Color image processing using cellular neural networks. TEES Progress Research Report 93-549 No. #2, Eindhoven: Philips Research.
Di, C. & Jess, J.A.G. (1994). On the development of a fast and accurate bridging fault simulator., 18 pp.
Erkelens, E.P. (1994). Improving the acoustic echo canceller with speech separation techniques., 40 pp.
Gijsbers, E. (1994). Development of an MPEG-2 system multiplexer., 50 pp.
Strik, M.T.J. (1994). Efficient code generation for application domain specific processors., 75 pp.

1990

Pineda de Gyvez, J. & Jess, J.A.G. (1990). The modeling of defects and faults. CEC Deliverable 4.1.1.jk EVEREST Task 4.1.1, February 15, 1990, Eindhoven: Philips Research.

1989

Pineda de Gyvez, J. & Jess, J.A.G. (1989). State of the art defect modelling, fault extraction and fault modeling. CEC Deliverable 4.1.1.jk EVEREST Task 4.1.1, Sept. 13, 1989, Eindhoven: Philips Research.
Pineda de Gyvez, J. (1989). Laser : a layout sensitivity explorer : report and user's manual. EUT Technical Report No. 89-E-216, Eindhoven: Technische Universiteit Eindhoven.

1988

Pineda de Gyvez, J. (1988). ALWAYS : a system for wafer yield analysis : report and users manual. EUT Technical Report No. 88-E-189, Eindhoven: Technische Universiteit Eindhoven.

1987

Vinck, A.J., Pineda de Gyvez, J. & Post, K.A. (1987). Implementation and evaluation of a combined test-error correction procedure for memories with defects. EUT-Report No. 87-E-169, Eindhoven: Technische Universiteit Eindhoven, 22 pp.

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Patent

2011

Haan, G. de & Bellers, E.B. (2011). Biased motion vector interpolation for reduced video artifacts. no US8073055.
Haan, G. de & Ciuhu, C. (2011). Motion estimation with video mode detection. no US7881500.
Haan, G. de & Damkat, C. (2011). Image scaling curve generation. no EP2382772.
Haan, G. de (2011). Motion-compensated image signal interpolation using a weighted median filter. no US7974342.
Haan, G. de, Biezen, P.W.A.C. & Wittebrood, R.B (2011). Image processing unit with fall-back. no US7949205.
Haan, G. de, Bruijn, F.J. & Meer, W.P. van der (2011). Mirror device. no EP2399245.
Haan, G. de, Velthoven, L.J. & Klompenhouwer, M.A. (2011). Display time control for images. no US8063920.
Damkat, C., Haan, G. de, Hofman, P.M. & kapadia, D. (2011). Method and apparatus for modifying an imgage by using a saliency map based on color frequency. no EP2411961.
Rocha Leitao, J.A. da & Haan, G. de (2011). Method and apparatus for generating enhanced images. no EP2389660.

2010

Haan, G. de (2010). Spatial signal conversion. no US7679676.
Haan, G. de, Bellers, E.B. & Janssen, J.W.G.M. (2010). Motion-compensated processing of image signals. no EP2057840.
Velthoven, L.J., Klompenhouwer, M.A. & Haan, G. de (2010). Edge dependent motion blur reduction. no US7643019.
Zjajo, A., Bergveld, H.J., Schuttert, R.F. & Pineda de Gyvez, J. (2010). Analog IC having test arrangement and test method for such an IC. no US7671618.

2009

Pineda de Gyvez, J., Gronthoud, A.G. & Amine, R. (2009). Testing radio frequency and analogue circuits. no US7539589.
Pineda de Gyvez, J., Gronthoud, A.G. & Cenci, C. (2009). Method and device for testing a phase locked loop. no US7477110.
Pineda de Gyvez, J., Pessolano, F., Meijer, M., Rius, J. & Rao, K.B.R. (2009). Real-time adaptive control for best IC performance. no US7500204.
Garg, M., Rao, K.B.R. & Pineda de Gyvez, J. (2009). Method for reducing power consumption in a state retaining circuit, state reaining circuit and electronic device. no US7577858.
Klompenhouwer, M.A., Haan, G. de & Velthoven, L.J. (2009). Unit for and method of sharpness enhancement. no US7489350.
Wittebrood, R.B, Haan, G. de & Lodder, R. (2009). Background motion vector detection. no US7519230.

2008

Haan, G. de & Berkel, C.H. van (2008). TV-PC Architecture. no EP1958082.
Haan, G. de & Berkel, C.H. van (2008). TV-PC Architecture. no US20080263184.
Haan, G. de & Bellers, E.B. (2008). Conversion of interlaced image signals into progressive scanned image signals. no EP1101354.
Haan, G. de & Ciuhu, C. (2008). Motion estimation. no EP1897376.
Haan, G. de & Ciuhu, C. (2008). Motion compensated De-interlacing with Film Mode Adaptation. no US20080259207.
Haan, G. de & Velthoven, L.J. (2008). Display time control for images. no US20080042953.
Haan, G. de (2008). Spatial resolution of video images. no US7206027.
Haan, G. de (2008). Motion Method for motion vector determination. no US20080144716.
Haan, G. de (2008). Pixel interpolation. no US20080063307.
Haan, G. de (2008). Enhancement of blurred image portions. no US20080025628.
Pineda de Gyvez, J. (2008). Method and apparatus for determining IDDQ. no US7336088.
Pineda de Gyvez, J. (2008). Circuit and method for controlling the threshold voltage of transistors. no US7332953.
Bellers, E.B. & Haan, G. de (2008). Motion estimation. no EP951781.

2007

Haan, G. de & Berkel, C.H. van (2007). TV-PC architecture (priority date: 30-11-2005; international filing date: 21-11-2006; international publication date: 07-06-2007). no WO2007063450.
Haan, G. de & Bellers, E.B. (2007). Chrominance signal interpolation. no EP 1095522 B1.
Haan, G. de (2007). Robust de-interlacing of video signals. no EP 1665781.
Bakker, J.N., Haan, G. de, Mevissen, P.G., Kettenis, J. & Ojo, O.A. (2007). Light Modulation removal. no US7227579.
Klompenhouwer, M.A., Haan, G. de & Velthoven, L.J. (2007). Unit for and method of calculating a sharpened edge. no EP 1512121 B1.
Velthoven, L.J., Klompenhouwer, M.A. & Haan, G. de (2007). Edge dependent motion blur reduction. no EP 1509881 B1.
Zjajo, A., Bergveld, H.J., Schuttert, R.F. & Pineda de Gyvez, J. (2007). Analog IC having test arrangement and test method for such an IC. no WO2007049210.

2006

Haan, G. de & Bellers, E.B. (2006). Biased motion vector interpolation for reduced video artifacts. no EP1627533 A2.
Haan, G. de & Bellers, E.B. (2006). Post-processing of interpolated images. no US7,136,107.
Haan, G. de & Bellers, E.B. (2006). Post-provessing if interpolated images. no EP1654872 A1.
Haan, G. de & Ciuhu, C. (2006). Motion compensated de-interlacing with film mode adaptation. no EP1714482 A1.
Haan, G. de & Ciuhu, C. (2006). Robust de-interlacing of video signals. no EP1665780 A1.
Haan, G. de & Cordes, C.N. (2006). Luminance and colour separation. no EP1639836 A1.
Haan, G. de & Hofman, M. (2006). Method and apparatus for rendering smooth teletext graphics. no EP1683353 A1.
Haan, G. de & Mertens, M. (2006). Motion estimator for reduced halos in MC up-conversion. no US7,010,039.
Haan, G. de & Pelagotti, A. (2006). Motion estimator for reduced halos in MC up-conversion. no US7,058,227.
Haan, G. de (2006). Robust de-interlacing of video signals. no EP1665781 A1.
Haan, G. de (2006). Estimating an edge orientation. no EP1627533 A2.
Haan, G. de (2006). Estimating an edge orientation. no EP1629435 A1.
Haan, G. de (2006). Motion-compensated image signal interpolation. no EP1647143 A1.
Haan, G. de (2006). Spatial image conversion. no EP1616300 A1.
Haan, G. de (2006). Spatial image conversion. no EP1616301 A2.
Haan, G. de (2006). Spatial signal conversion. no EP1636987 A1.
Fatemi, S.H., Mesman, B., Corporaal, H., Basten, A.A. & Kleihorst, R.P. (2006). SIMD with delay line in instruction bus. no PH005781.
Cordes, C.N. & Haan, G. de (2006). Luminance and colour separation. no EP1639835 A1.
Goel, S.K., Meijer, M. & Pineda de Gyvez, J. (2006). Test circuit and method for testing power switches. no PH0043096EP1.
Ojo, O.A., Kwaaitaal-Spassova, T.G. & Haan, G. de (2006). Electronic circuit and method for enhancing an image. no US7,009,662.
Tegenbosch, J.A.P. & Haan, G. de (2006). Image enhancement. no EP1661087 A1.
Wittebrood, R.B & Haan, G. de (2006). Motion vector field re-timing. no EP1661087 A1.

2005

Haan, G. de & Klompenhouwer, M.A. (2005). Anti motion blur display. no US6930676.
Haan, G. de & Klompenhouwer, M.A. (2005). Method of and unit for processing images. no US6501446.
Haan, G. de & Wittebrood, R.B (2005). Recognizing film and video objects occuring in parallel in single television signal fields. no US6937655.
Haan, G. de (2005). A unit for and method of image conversion. no EP1554874 A1.
Haan, G. de (2005). A unit for and method of image conversion. no EP1565878.
Haan, G. de (2005). A unit for and method of image scaling. no EP1547378 A1.
Haan, G. de (2005). Gamma correction. no EP1570651 A1.
Haan, G. de (2005). Method for image scaling. no EP1540593.
Haan, G. de, Biezen, P.W.A.C. & Wittebrood, R.B (2005). Image processing unit with fall-back. no EP1557037.
Haan, G. de, Klompenhouwer, M.A. & Velthoven, L.J. (2005). A unit for and method of sharpness enhancement. no EP1512120.
Klompenhouwer, M.A., Haan, G. de & Velthoven, L.J. (2005). Unit and method of calculating a sharpened edge. no EP1512120.
Riemens, A.K., Dommisse, A. & Haan, G. de (2005). Recognizing film and video occurring in parallel in television fields. no EP1574055 A1.
Velthoven, L.J., Klompenhouwer, M.A. & Haan, G. de (2005). Edge dependent motion blur reduction. no EP1509881.
Wesenbeeck, J.M.A. van, Haan, G. de, Klompenhouwer, M.A. & Krijn, M.P.C.M. (2005). CRT with enhanced vertical resolution. no EP1540689.
Wittebrood, R.B & Haan, G. de (2005). Image segmantation using template prediction. no EP1565879 A2.
Wittebrood, R.B & Haan, G. de (2005). Unit for and method of estimating a motion vector. no EP1514241.
Wittebrood, R.B & Haan, G. de (2005). Unit for and method of estimating a motion vector. no EP1514242.

2004

Haan, G. de & Klompenhouwer, M.A. (2004). Anti motion blur display. no EP 1402720.
Haan, G. de & Lodder, R. (2004). Improved spatial resolution of video images. no EP 1442426.
Bruijn, F.A. de, Bruls, W. & Haan, G. de (2004). Image coding with black dropping. no EP 1459563.
Bruls, W., Bruijn, F.A. de, Haan, G. de, Burazerovic, D. & Vervoort, G. (2004). Method and apparatus for motion compensated temporal interpolation of video sequences. no EP 1459553.
Lodder, R. & Haan, G. de (2004). Edge oriented interpolation of video data. no EP 1444824.
Mertens, M.J.W. & Haan, G. de (2004). Foreground/background detector. no US 6771799.
Peters, F.J., Haan, G. de & Gelissen, J.H.A. (2004). Conversion unit and method and image processing apparatus. no EP 1399883.
Stessen, J.H.C.J., Haan, G. de, Schutten, R.J. & Sijstermans, F.W. (2004). Video apparatus with noise reduction. no US 6714258.
Wittebrood, R.B & Haan, G. de (2004). Feature point selection. no EP 1435070.

2003

Haan, G. de & Bellers, E.B. (2003). De-interlacing image signals. no US6618094.
Haan, G. de & Klompenhouwer, M.A. (2003). Method and unit for displaying on image in sub-fields. no EP1285427.
Haan, G. de & Klompenhouwer, M.A. (2003). Method of and unit for far displaying an image in sub-fields. no US6614414.
Haan, G. de & Mertens, M.J.W. (2003). Motion estimator for reduced halos in motion compensated picture rate up-conversion. no EP1287492.
Haan, G. de & Wittebrood, R.B (2003). Recognizing film and video objects in parallel in single television signal fields. no EP1352528.
Haan, G. de, Bellers, E.B. & Schutten, R.J. (2003). Sub-pixel accurate motion vector estimation and motion-compensated interpolation. no US6639944.
Bakker, J.N., Haan, G. de, Kettenis, J., Mevissen, P.G., Ojo, O.A. & Raay, J.H.J.M. van (2003). Camera with light modulation removing means. no EP1281276.
Bruls, W.H.A., Camiciotti, L., Haan, G. de, Kleihorst, R.P. & Werf, A. van der (2003). Noise filtering on image sequence. no EP1316206.
Mertens, M.J.W. & Haan, G. de (2003). Image foreground/backgroundvelocity detector. no EO1290639.
Timmer, A.H., Harmsze, F. & Meerbergen, J. van (2003). Data processorutilizing set-associative cache memory for stream and non-stream memory addresses.

2002

Haan, G. de & Bellers, E.B. (2002). Chrominance signal interpolation. no US6498609.
Haan, G. de & Klompenhouwer, M.A. (2002). Method and unit for processing images. no EP1194919.
Haan, G. de & Pelagotti, A. (2002). Problem area location in an image signal. no US6487313.
Haan, G. de, Biezen, P.W.A.C. & Ojo, O.A. (2002). Adaptive picture delay. no US6411341.
Haan, G. de, Huijgen, G., Biezen, P.W.A.C. & Ojo, O.A. (2002). Picture signal processing mode control. no EP1217829.
Haan, G. de, Schutten, R.J. & Pelagotti, A. (2002). Motion estimation and motion compensated interpolation. no US6385245.
Bellers, E.B. & Haan, G. de (2002). Motion estimation. no US6445741.
Ojo, O.A., Kwaaitaal-Spassova, T.G. & Haan, G. de (2002). Electronic circuit and method for enhancing an image. no EP1232649.

2001

Haan, G. de (2001). Camera with light modulation removing means. no WO0176234.
Haan, G. de (2001). Chrominance signal interpolation. no EP1095522.
Haan, G. de (2001). Conversion of interlaced image signals into progressive scanned. no EP1101354.
Haan, G. de (2001). Electronic circuit and method for enhancing an image. no WO0174056.
Haan, G. de (2001). Estimation of movements in video images. no EP1152512.
Haan, G. de (2001). Estimation of movements in video images. no WO0145422.
Haan, G. de (2001). Foreground/background detector. no WO0189225.
Haan, G. de (2001). Method and apparatus for motion vector processing. no US6208760.
Haan, G. de (2001). Method and unit for processing images. no WO0139488.
Haan, G. de (2001). Method of and unit for displaying an image in sub-fields. no WO0186617.
Haan, G. de (2001). Motion estimation in vedeo images. no WO0145421.
Haan, G. de (2001). Motion estimation in video images. no WO0145420.
Haan, G. de (2001). Motion estimation. no US6278736.
Haan, G. de (2001). Motion estimation. no US6289051.
Haan, G. de (2001). Motion estimator for reduced halos in MC up-conversion. no WO0188852.
Haan, G. de (2001). Motion vector estimation and detection of covered/uncovered image parts. no US6219436.
Haan, G. de (2001). Noise filtering an image sequence. no WO0197509.
Haan, G. de (2001). Sub-pixel accurate motion vector estimation and motion-compensated. no EP1090502.
Haan, G. de (2001). Video-apparatus with noise reduction. no EP1137268.
Groeneveld, P.R. (2001). Method of Designing a Constraint Driven Integrated Circuit Layout. no US 6230304.

2000

Haan, G. de & Pelagotti, A. (2000). Problem area location in an image signal. no EP1048170.
Haan, G. de (2000). Noise filtering. no US06115502.
Haan, G. de (2000). Video signal processing. no US06122016.
Haan, G. de (2000). Video signal scan conversion. no US06034734.

1999

Eijk, C.A.J. van (1999). System and method for logic rectification based on connection reuse.
Kastrup, B. & Meerbergen, J. van (1999). Reconfigurable processor data-path with configuration cache based on content addressable memories.
Theis, J.P., Nowak, K. & Meerbergen, J. van (1999). Next generation reconfigurable computing cell for FPGA.

1998

Eijndhoven, J.T.J. van, Slavenburg, G.A. & Rathnam, S. (1998). VLIW processor processes commands of different widths.

1997

Leijten, J.A.J., Meerbergen, J. van & Timmer, A.H. (1997). Signal processing device.
Timmer, A.H., Leijten, J.A.J. & Meerbergen, J. van (1997). Signal processing device and method of planning connections between processors in a signal processing device.

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Dissertation

2012

Jan, Y. (2012). Quality-driven model-based design of multi-processor accelerators : an application to LDPC decoders. Eindhoven: Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr. J. Pineda de Gyvez, dr.ir. L. Jozwiak).

2011

Funk, M. & Funk, M. (2011). Model-driven design of self-observing products. Eindhoven: Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr. H. Corporaal, prof.dr.ir. A.C. Brombacher, dr ing P.H.A. van der Putten).
Shabbir, A. (2011). Predictable multi-processor system on chip design for multimedia applications. Eindhoven: Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr. H. Corporaal, dr.ir. B. Mesman, dr.ir. Akash Kumar).

2010

Akesson, K.B. (2010). Predictable and composable system-on-chip memory controllers. Eindhoven: Technische Universiteit. ((Co-)promot.: prof.dr. K.G.W. Goossens, prof.dr. H. Corporaal).
Heesch, F.H. van (2010). Video processing for LCD-TVs. Eindhoven: Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr.ir. G. de Haan).
Hu, H. (2010). Video enhancement : content classification and model selection. Eindhoven: Technische Universiteit. ((Co-)promot.: prof.dr.ir. G. de Haan, prof.dr.ir. R.H.J.M. Otten).
Zjajo, A. (2010). Design and debugging of multi-step analog to digital converters. Eindhoven: Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr. J. Pineda de Gyvez).

2009

Kumar, Akash (2009). Analysis, design and management of multimedia multiprocessor systems. Eindhoven: Technische Universiteit. ((Co-)promot.: prof.dr. H. Corporaal, dr.ir. B. Mesman, Y. Ha).
Hansson, M.A. (2009). A composable and predictable on-chip interconnect. Eindhoven: Technische Universiteit. ((Co-)promot.: prof.dr. H. Corporaal, prof.dr. K.G.W. Goossens).
Hoes, R.J.H. (2009). Configuring heterogeneous wireless sensor networks under quality-of-service constraints. Eindhoven: Technische Universiteit. ((Co-)promot.: prof.dr.ir. A.A. Basten, prof.dr. H. Corporaal, C.K. Tham).
Moonen, A.J.M. (2009). Predictable embedded multiprocessor architecture for streaming applications. Eindhoven: Technische Universiteit. ((Co-)promot.: prof.dr.ir. R.H.J.M. Otten, prof.dr. H. Corporaal).
Westra, H.J.L. (2009). Congestion analysis and management. Eindhoven: Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr.ir. P.R. Groeneveld, prof.dr.ir. R.H.J.M. Otten).

2008

Beric, A. (2008). Video post processing architectures. Eindhoven: Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr.ir. G. de Haan, prof.dr.ir. J. van Meerbergen, ir. J.A.J. Leijten, prof.dr. H. Corporaal, prof.dr.ir. R.H.J.M. Otten).
Ciordas, C. (2008). Monitoring-aware network-on-chip design. Eindhoven: Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr. H. Corporaal, prof.dr.ir. A.A. Basten, prof.dr.ir. R.H.J.M. Otten).
Florescu, O. (2008). Predictable design for real-time systems. Eindhoven: Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr. H. Corporaal, dr.ir. J.P.M. Voeten).
Ghamarian, A.H. (2008). Timing analysis of synchronous data flow graphs. Eindhoven: University Press. ((Co-)promot.: prof.dr.ir. R.H.J.M. Otten, prof.dr.ir. A.A. Basten, dr.ir. M.C.W. Geilen).
Poplavko, P. (2008). An accurate analysis for guaranteed performance of multiprocessor streaming applications. Eindhoven: University press. ((Co-)promot.: prof.dr.ir. R.H.J.M. Otten, prof.dr.ir. A.A. Basten, prof.dr.-ing. J.A.G. Jess).

2007

Stuijk, S. (2007). Predictable mapping of streaming applications on multiprocessors. Eindhoven: TUE Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr. H. Corporaal, prof.dr.ir. J. van Meerbergen, prof.dr.ir. A.A. Basten).
Fatemi, S.H. (2007). Processor architecture design for smart cameras. Eindhoven: Eindhoven University Press. ((Co-)promot.: prof.dr. H. Corporaal, prof.dr.ir. A.A. Basten, dr.ir. B. Mesman).
Gheorghita, Valentin (2007). Dealing with dynamism in embedded system design. Eindhoven: TUE Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr. H. Corporaal, prof.dr.ir. A.A. Basten).

2006

Zhao, M. (2006). Video Enhancement using Content-Adaptive Least Mean Square Filters. Eindhoven: University Press. ((Co-)promot.: prof.dr.ir. G. de Haan, prof.dr.ir. R.H.J.M. Otten, prof.dr.ir. J. van Meerbergen).

2005

Huang, J. (2005). Predictability in Real-Time Software Design. Eindhoven. ((Co-)promot.: prof.dr.ir. R.H.J.M. Otten, prof.dr. H. Corporaal, dr.ir. J.P.M. Voeten).

2004

Naidu, S.R. (2004). Tuning for Yield. Towards predictable deep-submicron manufacturing. Eindhoven: Universiteitsdrukkerij TU Eindhoven. ((Co-)promot.: prof.dr.ir. R.H.J.M. Otten, prof.dr.-ing. J.A.G. Jess, prof.dr.ir. P.R. Groeneveld, prof.dr.ir. J. van Meerbergen).

2003

Zhao, Q. (2003). Static Resource Models for Code Generation of Embedded Processors. Eindhoven: Universiteitsdrukkerij TU Eindhoven. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr.ir. J. van Meerbergen, dr.ir. B. Mesman).

2002

Alba Pinto, C.A. (2002). Storage constraint satisfaction for embedded processor compilers. Eindhoven: TU/e. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr.ir. J. van Meerbergen, dr.ir. B. Mesman, prof.dr.ir. R.H.J.M. Otten, prof.dr. H. Corporaal).

2001

Mesman, B. (2001). Constraint analysis for DSP code generation. Eindhoven: Universiteitsdrukkerij TU/e. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr.ir. J. van Meerbergen, prof.dr. H. Corporaal).
Jacobs, E.T.A.F. (2001). Power Dissipation and Timing in CMOS Circuits. Eindhoven: Universiteitsdrukkerij TU Eindhoven. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr.ir. R.H.J.M. Otten).

2000

Rensink, A.M. (2000). Prototyping of embedded systems, an analysis of industrial approaches aimed at reducing time-to-market. 's-Hertogenbosch: A.M. Rensink. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.ir. M.P.J. Stevens).
Rutten, J.W.J.M. (2000). Burst-Mode Finite State Machines. Eindhoven: Universiteitsdrukkerij Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof. S.M. Nowick, dr.ir. M.R.C.M. Berkelaar).

1999

Janssen, G.L.J.M. (1999). Logics for digital circuit verification: Theory, algorithms and applications. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr. J.C.M. Baeten, dr.ir. C.A.J. van Eijk).
Schoenmakers, P.J. (1999). Supporting the evolution of software. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr. P. Marwedel, dr.ir. C.A.J. van Eijk).

1998

Leijten, J.A.J. (1998). Real-time constrained reconfigurable communication between embedded processors. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr.ir. J. van Meerbergen).
Villar dos Santo, L.C. (1998). Exploiting instruction-level parallelism : a constructive approach. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr.ir. J. van Meerbergen, dr.ir. C.A.J. van Eijk).

1997

Eijk, C.A.J. van (1997). Formal methods for the verification of digital circuits. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr. J.C.M. Baeten, dr.ir. M.R.C.M. Berkelaar).

1996

Fleurkens, J.W.G. (1996). Interactive modelling and simulation of heterogeneous systems. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.ir. M.P.J. Stevens, dr.ir. J.T.J. van Eijndhoven).
Heijligers, M.J.M. (1996). The application of genetic algorithms to high-level synthesis. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr.ir. W.M.G. van Bokhoven, dr.ir. J.T.J. van Eijndhoven).
Huijbregts, E.P. (1996). A complete design path for the layout of flexible macros. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr.ir. R.H.J.M. Otten, dr.ir. J.T.J. van Eijndhoven).
Hurk, J.A.A.M. van den (1996). Hardware/software codesign: an industrial approach. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.ir. M.P.J. Stevens, dr.ir. J.F.M. Theeuwen).
Timmer, A.H. (1996). From design space exploration to code generation: a constraint satisfaction approach for the architecture synthesis of digital VLSI circuits. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr. E.H.L. Aarts, dr.ir. M.R.C.M. Berkelaar).

1995

Di, C. (1995). The modelling and simulation of defect induced faults in CMOS IC's. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.ir. M.T.M. Segers, dr.ir. J.F.M. Theeuwen).
Philipsen, W.J.M. (1995). Optimization with potts neural networks in high level synthesis. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr.ir. W.M.G. van Bokhoven, dr.ir. J.T.J. van Eijndhoven).

1992

Goossens, K.G.W. (1992). Embedding Hardware Description Languages in Proof Systems. Edinburgh: University of Edinburgh. ((Co-)promot.: S. Anderson, M. Fourman).

1991

Pineda de Gyvez, J. (1991). IC defect-sensitivity : theory and computational models for yield prediction. Eindhoven: Technische Universiteit Eindhoven. ((Co-)promot.: prof.dr.-ing. J.A.G. Jess, prof.dr.ir. W.M.G. van Bokhoven, dr.ir. J.F.M. Theeuwen).