RTMemController is an open-source tool for evaluating the worst-case and average-case execution time of memory transactions, which are executed by dynamically scheduling memory commands to DDR3 SDRAMs. This tool is based on the dynamic command scheduling algorithm proposed in . It uses the mathematical formalization of the algorithm, which has been shown to produce cycle-accurate timing behavior to a memory controller implementation in SystemC. The following sections introduce how this tool is developed and how to use it to achieve worst-case and average-case execution time results.
RTMemController includes two parts, a memory trace processor and a command scheduler. The former is responsible for providing a memory trace that contains the transactions executed by the memory controller. The memory trace is generated by combining a number of memory traces that are specified by the user. Each of them represents the memory trace from a requestor, e.g., a processor, a DMA controller or an accelerator, etc. The scheduler executes the transactions by dynamically scheduling commands according to the proposed algorithm in , which respects the timing constraints in the JEDEC DDR3 standard.
The memory trace processor is implemented in the Python language. It reads the memory traces specified by the user, each of which represents a requestor that produces memory transactions. This tool uses a simple first-come first-serve (FCFS) mechanism. As a result, the memory trace processor combines the specified traces into a single combined trace according to the time stamps of the transactions. The generated memory trace provides a list of transactions that are executed by the memory controller. For users’ preferring arbitration policies for transactions from different requestors, it is easy to replace this memory trace processor with their own traces.
The command scheduler executes each transaction by dynamically scheduling memory commands subject to relevant DDR3 timing constraints. It is implemented based on Equations (3) to (7) in our paper , which capture the scheduling dependencies caused by the timing constraints for different commands. The scheduler collects the actual execution time of each transaction based on the command scheduling results. The maximum execution time of a transaction with particular size is collected as the measured WCET. Moreover, the worst-case execution time (WCET) of a transaction is given by two means which result in a scheduled WCET and an analytical WCET. The former is obtained by dynamically scheduling commands according to the worst-case initial bank states that are based on as-late-as-possible (ALAP) scheduling. The latter is simply given by the theorems in . The analytical and scheduled WCET results are independent from the input memory traces. However, the measured WCET is dependent on the input traces.
How to use:
requires user's inputs of memory traces and memory specification. The following command format can be used to generate a combined trace file.
traces.py [-h] [--outfile OUTFILE] traces [traces ...]
For example, if a user chooses the provided Mediabench applications gsmdecode, epic, unepic and jpegencode, and the size of the transactions is 128 bytes, the following command is used to generate the combined trace file "combinedTrace.dat".
python traces.py --outfile combinedTrace.dat memtraces/mediabench-gsmdecode_128.armtrace memtraces/mediabench-epic_128.armtrace memtraces/mediabench-unepic_128.armtrace memtraces/mediabench-jpegencode_128.armtrace
Note that it is flexible for users to choose any traces with either fixed or variable transaction sizes. In addition, it supports adding users' traces rather than the limited number of provided Mediabench application traces.
After the combined trace is generated, it is used by the scheduler to execute each transaction in the trace. The command format of the scheduler is as follows.
./cmdScheduler [-m] memorySpec [-t] transTrace
For example, to use a DDR3-800 SDRAM and we have a trace with fixed transaction, e.g., 128 Bytes, the following command is used to run the command scheduler.
./cmdScheduler -m memspecs/JEDEC_2Gb_DDR3-800D_16bit -t combinedTrace.dat
Note that users can add more DDR3 memory specifications in addition to the limited number of the given DDR3 memory specifications. DRAMPower
) has provided more memory specifications, from which users can make their own for using this tool.
Finally, the command scheduling results of each transaction are collected and they are included in the analyticalSchedulingResult.dat file. Moreover, the measured, analytical and scheduled WCET and average execution time results are given by the StatisticsResult.dat file which also presents some statistics results. Those two files are included in the "results/" folder.
If you decide to use RTMemController in your research, please cite one of the following references.
To cite WCET analysis of dynamic command scheduling
 Dynamic Command Scheduling for Real-Time Memory Controllers
Yonghui Li, Benny Akesson, and Kees Goossens
In Proc. Euromicro Conference on Real-Time Systems (ECRTS), 2014. [pdf]
To cite the architecture and algrithms of the dynamically-scheduled memory controller as well as the WCRT/WCET analysis
 Architecture and Analysis of a Dynamically-Scheduled Real-Time Memory Controller
Yonghui Li, Benny Akesson, and Kees Goossens
In: Real-Time Systems, 2015. [pdf]
To cite the RTMemController tool
 RTMemController: Open-source WCET and ACET analysis tool for real-time memory controllers
Yonghui Li, Benny Akesson, and Kees Goossens
This tool is released now under the BSD 3-Clause License. This gives the users and developers the flexibility to employ, develop and re-distribute the source code with minimal obligations. We only ask users to cite one of the above references.
You may use the software subject to the license terms below provided that you ensure that this notice is replicated unmodified and in its entirety in all distributions of the software, modified or unmodified, in source code.
Copyright (c) 2014 Eindhoven University of Technology and Czech Technical University in Prague
All rights reserved.
Redistribution and use in source form with or without modification are permitted provided that the following conditions are met:
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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By clicking the 'Download' button below, you acknowledge that you have read, understood and accepted to use RTMemController under the terms of license detailed above. The current version of the tool is v1.2 and was released on 21th Jan., 2015.
The Manual file has more detailed information of RTMemController. It can be downloaded from here
Timed Automata Model:
A Timed Automata (TA) model of the same real-time memory controller as RTMemController can be downloaded from here
You are very welcome to forward your questions to Yonghui Li
at yonghui.li [at] tue.nl
RTMemController-v1.1 was released on Oct. 29, 2014. A memory bug was fixed based on the feedback from Danlu Guo who is working at the University of Waterloo. The feedback is appreciated!
RTMemController-v1.2 was released on Jan. 21, 2015. The result folder is automatically created, such that users can easily find the results of worst-case and average-case execution times.
The dynamically-scheduled memory controller implemented by RTMemController has been modeled by an accurate Timed Automata model, which was publicly online on Oct. 15, 2015. The TA model supports
simulation, validation, and verification. It provides both worst-case response time and worst-case bandwidth of the memory controller.