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In the framework of the CHESS project, we have developed a hardware independent method to evaluate the performance of parallel VHDL simulation. The method enables us to measure the performance of different parallel simulation algorithms on parallel architectures with different characteristics. Instead of running the simulation on existing hardware platforms, our method uses a architecture simulator on a normal workstation. Currently our research is focussed on the simulation of VHDL, but the design can be modified for other kinds of simulation.
Figure shows the method we use to collect statistics of the parallel VHDL simulation. Top-down, the following tools are involved:
Other partners in the CHESS project have composed a set of benchmarks to measure the performance of parallel VHDL simulation . We will use these benchmarks to evaluate the simulation algorithms and network topologies.
Section provides a short introduction to VHDL, section describes the VHDL to C++ compiler, section describes the workings of the parallel simulation kernel, section describes the architecture simulation, and section concludes the discussion.