Previous: Analysis of Parallel VHDL Simulation Up: Analysis of Parallel VHDL Simulation Next: VHDL


In the framework of the CHESS project, we have developed a hardware independent method to evaluate the performance of parallel VHDL simulation. The method enables us to measure the performance of different parallel simulation algorithms on parallel architectures with different characteristics. Instead of running the simulation on existing hardware platforms, our method uses a architecture simulator on a normal workstation. Currently our research is focussed on the simulation of VHDL, but the design can be modified for other kinds of simulation.

Figure shows the method we use to collect statistics of the parallel VHDL simulation. Top-down, the following tools are involved:

The compiler partitions the VHDL source and compiles it into C++. This results in a number of parallel runnable C++ programs that have compiled-in information about other partitions needed for message passing.

The parallel kernel (parker) contains the simulation algorithms both for the internal VHDL simulation and the global parallel simulation. One C++ program and a parker form a partition (the dashed boxes in Figure ) that denotes the code for one network node.

The architecture simulator (archsim) simulates the underlying network and keeps accounting information of the execution times of the processors. The nodes of the simulated network are simulated by the partitions.

In our framework, all the tools together with the generated C++ are compiled into one executable. The executable can give a wide range of data, both simulation-dependent and network-dependent.

Other partners in the CHESS project have composed a set of benchmarks to measure the performance of parallel VHDL simulation [3]. We will use these benchmarks to evaluate the simulation algorithms and network topologies.

Section provides a short introduction to VHDL, section describes the VHDL to C++ compiler, section describes the workings of the parallel simulation kernel, section describes the architecture simulation, and section concludes the discussion.