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Because it is impossible to provide a complete overview of VHDL in a short space, we only outline the main characteristics needed to understand the aspects typical to VHDL simulation. Figure shows a small example of a circuit.
Every circuit in VHDL consists of a number of processes interconnected by signals. A signal can be seen as a wire running from one process to another.
Every process has a description in the form of sequential code. This code describes how the process reacts to changes on incoming signals and how it drives outgoing signals. The code that is used in these sequential parts is very similar to Ada, augmented with a number of typical VHDL features, the most important being the wait statement and the waveform assignment. They are used in the following example:
entity Nor_Gate is port( a, b: in Bit; y: out Bit ); end Nor_Gate;In this example we can see the definition of an entity called quot;Nor_Gatequot;. This entity has an interface consisting of two incoming signals and one outgoing signal, as specified by the quot;portquot;-clause. Below the definition of the entity, an implementation is defined, consisting of one process that contains two statements:
architecture demo of Nor_Gate is begin process begin y <= a nor b after 10 ns; wait on a, b; end process; end demo;
After the initialisation of all values, and the execution of every process until it suspends, the simulation cycle starts. It consists of two separate phases: