Index of /~heco/courses/EmbeddedComputerArchitecture

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[TXT]5kk73-2010.html2011-09-15 17:08 25K 
[TXT]5kk73-2011.html2012-11-13 16:13 23K 
[TXT]5kk73-2012.html2013-11-12 18:05 26K 
[TXT]5kk73-2013.html2014-09-02 18:31 28K 
[TXT]5kk73-2014.html2015-01-16 12:38 27K 
[   ]20130107-5kk73-noc_v1.pdf2013-01-17 18:30 7.1M 
[   ]ASIP.ppt2012-10-15 14:07 816K 
[   ]Accelerators 2014.pptx2014-11-11 11:43 4.0M 
[   ]Architecture-modeling.ppt2011-01-14 13:42 1.3M 
[IMG]BeagleBoard.jpg2010-08-29 22:37 37K 
[   ]Cache-Recap.pptx2014-11-18 18:10 662K 
[   ]Caches-Analogy.pptx2014-11-18 18:10 2.1M 
[   ]Ch4-DLP-Vector-SIMD-GPU.pptx2015-01-13 21:14 4.6M 
[   ]DMMa.ppt2013-11-26 15:52 1.7M 
[   ]DMMb.ppt2012-12-10 16:41 4.0M 
[   ]DMMc.ppt2014-01-06 00:23 1.7M 
[   ]DMMd.ppt2012-01-13 13:01 414K 
[   ]DSP.ppt2010-09-06 18:44 525K 
[   ]Design and Verify.pdf2013-01-17 18:35 1.4M 
[   ]Design and Verify SIMULINK.pdf2012-01-17 19:26 1.6M 
[   ]GPU.ppt2010-11-08 12:22 15M 
[   ]GPU2011.pptx2011-11-28 12:52 4.2M 
[   ]GPU2012.pptx2012-11-22 18:45 6.9M 
[   ]Goossens-NoC.pdf2014-01-13 11:55 7.1M 
[   ]Goossens_2004-interconnectcentric-chap15.pdf2010-11-29 17:57 286K 
[   ]Goossens_mpsoc-casestudy.pdf2010-11-30 15:53 4.0M 
[   ]IEEEDT-catthoor.pdf2010-08-29 22:37 250K 
[   ]IEEEDT-nachtergaele.pdf2010-08-29 22:38 182K 
[   ]IEEEDT-ranjan_panda.pdf2010-08-29 22:38 176K 
[   ]ILP-compilation.ppt2011-10-21 16:14 629K 
[   ]ILP.ppt2013-12-11 17:01 1.7M 
[   ]Lab1-AES.pptx2012-10-16 12:54 509K 
[   ]MIPSdetails.ppt2013-11-12 18:05 5.5M 
[   ]MIPSdetails.pptx2014-09-02 18:45 2.1M 
[   ]MPSoC-CELL.ppt2010-10-13 12:07 3.5M 
[   ]MultiProcessing-old.ppt2012-01-19 19:13 525K 
[   ]MultiProcessing.ppt2015-01-16 12:38 1.3M 
[   ]NOC-KeesGoossens.pdf2011-12-06 17:47 7.4M 
[   ]NOC.pdf2015-01-16 12:36 7.1M 
[   ]Nugteren-MemoryAccessPatterns.pdf2013-11-13 09:36 3.0M 
[   ]RISC-overview.ppt2010-09-06 10:35 816K 
[   ]Real-Time SDRAM controllers.pdf2011-12-02 16:08 4.5M 
[   ]SDRAM.pptx2013-11-21 22:47 2.8M 
[   ]SIMD-XETAL+IMPA.ppt2011-01-14 13:02 3.1M 
[TXT]Schedule2010.html2011-02-24 17:52 69K 
[TXT]Schedule2011.html2012-01-10 10:42 42K 
[TXT]Schedule2012.html2012-11-21 14:49 41K 
[   ]Schedule2013.xlsx2013-11-12 18:44 15K 
[   ]Schedule2014.xlsx2014-09-02 18:39 15K 
[   ]SimulinkForEmbeddedSystems.pdf2011-01-11 11:10 718K 
[   ]TIM2_Guide.pdf2011-10-21 14:08 585K 
[   ]TIM_and_HSD_languages_3_v1.1.pdf2012-11-10 23:10 824K 
[   ]VLIW-architecture.ppt2014-09-25 08:38 2.1M 
[   ]VLIW-compilation.ppt2014-11-18 18:10 933K 
[   ]VLIW.ppt2012-10-08 15:29 1.8M 
[   ]Wijtvliet-Accelerators.pdf2013-11-12 18:11 1.1M 
[   ]WrapUp.ppt2015-01-16 12:36 15M 
[   ]Ye-GPU2013.pptx2013-11-12 18:25 6.0M 
[   ]asip_2013.ppt2013-11-14 17:40 874K 
[   ]chapter2.pdf2010-08-29 22:37 205K 
[   ]course-description.doc2010-08-29 22:37 49K 
[   ]diguet.ps2010-08-29 22:37 204K 
[   ]loop-trafos.ppt2011-11-29 18:14 465K 
[   ]looptransMP03small.pdf2013-12-06 17:36 1.5M 
[   ]looptransMP05.pdf2014-12-04 17:27 2.3M 
[IMG]mica2dot.jpg2010-08-29 22:38 28K 
[   ]mpsoc_CELL.ppt2012-01-19 19:09 2.8M 
[   ]mpsoc_realtime.ppt2013-01-07 13:20 1.9M 
[   ]neuralarchitectures.pdf2012-11-26 16:38 6.2M 
[   ]neuralarchitectures04.pdf2014-01-30 16:43 5.6M 
[   ]neuralarchitectures05.pdf2014-12-18 10:17 6.2M 
[   ]overview.ppt2014-09-02 18:44 3.4M 
[   ]sdram_12-11-2012.pptx2012-11-13 16:17 2.3M 
[   ]sdram_20-11-2014.pdf2015-01-26 12:48 2.4M 

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