by Henk Corporaal
Eindhoven University of Technology (TU/e)
April 2016
Note: in the following list we use the abbreviations:
- ES: Embedded Systems Master at TU/e
- EE: Electrical Engineering Master at TU/e
1.
Arno Tiemersma, ES
Constrained based code generation for
CGRAs
2.
Vishnu Pasupula, ES, 2016
Scheduling and optimization of production
printers
With Oce Venlo
3.
Sander Vocke, ES, 2016
Halide to C to SiliconHive / Intel Image
Processing Unit
With Intel Eindhoven
4.
Jumana Mundichipparakkal, ES, 2016
Fast binary simulation by binary
translation
With Intel Eindhoven
5.
Bart van Dongen, EE, 2016
Video distribution system
With Prodrive Einhoven
6.
Sandeep Poddar, ES, 2016
SKA Power Modelling
With ASTRON Dwingeloo
7. Mattia Fiumara, EE, 2016
Convolutional Neural Networks on SIMD
systems
8.
Jos IJzerman, ES, 2016
Vector support for Convolutional Neural
Networks on Transport Triggered Architectures
With Tampere University of Technology, Finland
9.
Michael Adriaansen, ES, 2016
LLVM based Compiler support for CGRAs
(Coarse Grain Reconfigurable Arrays)
10.
Stef van Son, ES, 2016
OpenVX support for Intel processing
platform
With Intel Eindhoven
11.
Stef Louwers, ES, 2016
Multi-granularity arithmetic for CGRAs
12.
Roel Oomen, EE, 2016
Technology scaling prediction
With IMEC Eindhoven
13.
Ozgun Yalcinkaya, ES, 2016
Video (TV) enhancement
With Sigma-Design, Waalre
14.
Gaurav Raina, ES, 2016
Mapping Convolutional Neural Networks on
a Heterogeneous Multi-Core
With RECORE, Enschede
15.
Thomas Sioutas, ES, 2015
Many core DSP system mapping support
With Prodrive
16.
Peter Koek, EE, 2015
DLP exploitation for SDF modelled applications
With NXP
17.
Matthias Schneider, ES, 2015
Re-entry satelites: embedded system
design
With DLR (Deutsches Zentrum für Luft- und Raumfahrt), Bremen
18.
Wishnu Pramadi, ES, 2015
Automatic code generation for the ConvNet
accelerator
19.
Thieme Joziasse, ES, 2015
Face detection and tracking on GPU based
system
With Altran, Eindhoven
20.
Bas Renet, EE, 2015
Advanced debugging functionality for
secure identification smart cards
With NXP, Eindhoven
21.
Grigoris Raptis, EE, 2015
High-speed servo implementation on a
hybrid (ARM/FPGA SoC) processing system
With ASML, Velthoven
22.
Han Lin, ES, 2014
Low power memory system HW-SW co-design
for wireless sensor node
With IMEC Eindhoven
23.
Miguel Emilio Oznaya Angeles, Emb
Systems, 2014
GPU-based real-time holography through
time-domain signal processing
With Sorama, Eindhoven
24.
Petros Voudouris, ES, 2014
Real-time GPU processing
25.
Wouter Ouwens, EE, 2014
Real-time contactless vibration detection
with NAH in lithography systems using a GPU.
With Sorama, Eindhoven
26.
Shyam Balasubramanian, ES, 2013
Store-and-Forward Networking Solutions with Autonomous Aerial Vehicles
With THALES, Huizen
27.
Koen Hausmans, ES, 2013
Reducing Synchronization Overhead by Scaling Parallel Streaming
Applications
With NXP
28.
Yannick van Bavel, ES, 2013
Advanced ultrasound beam forming using
GPGPU technology
With eSaote
29.
Ruizhou Xie, ES, 2013
Flexible memory shuffling unit for a programmable neural processor
30.
Rick Hilkens, EE, 2013
Implementation and analysis of a
real-time adaptation algorithm on an FPGA for steering a nonliniear
interference suppressor
With EE-SPS
31.
Peter Broere, ES, 2013
A memory-centric SIMD neural network
accelerator: Balancing efficiency & flexibility
32.
Martijn van den Dungen, ES, 2013
Vision-based edge tracking for area
optimization
With OTB, Eindhoven
33.
Luc Waeijen, ES, 2013
Design Space Exploration of a Low-Energy Wide-SIMD
34.
Hoisun Ng, ES, 2013
Design and Evaluation of a Novel Programmable Accelerator for Digital
Signal Processing
With IBM Zurich
35.
Luuk Mallens, ES, 2013
A framework for data-access strategies in
GPGPU programs
With VectorFabrics
36.
Sunil John, ES, 2012
Parallel code generation for
non-preemptively scheduled multiprocessor systems
With NXP
37.
Sohan Nandkumar Walimbe, ES, 2012
Architectural leakage power minimization
of scratchpad memories by application-driven subbanking
With IMEC-NL
38.
Pieter Custers, EE, 2012
Algorithmic species: classifying program
code for parallel computing
39.
Roy van Doormaal, ES, 2012
Parallel training of large scale neural
networks: Performance Analysis & Prediction
40.
Luuk Loeffen, EE, 2012
Automated generation of IP Core wrapper
for faster SoC integration using HLS
With NXP
41.
Twan Kamp, EE, 2012
Dataflow-based Multi-ASIP Motion Control
Platform on Chip
With ASML
42.
Johan Hendriks, ES, 2012
High Level Synthesis: Performance
Analysis and Code Optimization
43.
Luke Lemmen, ES, 2012
FPGA Firmware Qualification Framework; Using
AXI Interconnect and Extended Debug Facilities
With Prodrive, Eindhoven
44. Sheng Hao Wang, EE, 2012
Saliency Detection on FPGA Using
Accelerators and Evaluation of Algorithmic Skeletons
45. Rik Jongerius, EE, 2012
Quantifying and Capturing the Semantics
of Computational Problems in Contemporary Applications for Algorithmic Choice
With IBM research, Zurich
46.
Martien Spierings, ES, 2011
Embedded platform selection based on the
Roofline model; Applied to video content analysis
With Prodrive (together with Rob vd Voort)
47.
Rob van de Voort, ES, 2011
Embedded platform selection based on the
Roofline model; Applied to video content analysis With Prodrive (together
with Martien Spierings)
48.
Tim Vriends, ES, 2011
Evaluation of High Level Synthesis for
the implementation of Marker Detection on FPGA
49.
Xuyuan Jin, EE, 2011
Automatic Code Generation and Adaptive
Grid Scheduling for GPU Cluster Computing
50.
Levent Korkut, ES, 2011
Hybrid Sensor Systems for Cost Efficient
Egomotion Estimation
With Philips Research
51.
Shubhendu Sinha, ES, 2011
Clustering
Synchronous Dataflow Actors for finding Optimal Configuration of Configurable
Hardware for Multiple Applications
With NXP
52. Michiel Bosveld, ES, 2011
Exploring the design space of a VLIW
processor for LTE and LTE-A
With STEricsson
53.
Jarno van der Sanden, ES, 2011
Evaluating the Performance and
Portability of OpenCL
54.
Wilco Belgraver Thisse, EE, 2011
A comparative study of optical depth
sensors for user interaction
With Philips Research
55.
Jingzhou Luo, EE, 2011
A Low Cost Programmable LIW-SIMD
Coprocessor for Filters and MAC-related
Algorithms
With STEricsson
56.
Mark Wijtvliet, ES, 2011
Design of a multi-electrode fish
recognition system based on changing cross-sectional resistance
With Witteveen&Bos
57. Kris Hoogendoorn, EE, 2011
Inter-cluster Communication on Clustered
SIMD Architectures
58.
Martijn Koedam, EE, 2011
Exploiting Inter and Intra Application
Dynamism through System-Scenarios to Save Energy
59.
Ronald van Gastel, EE, 2011
Evaluation and mapping of hierarchical-temporal
memory networks on an efficient platform
60.
Tim van den Kerkhof, EE, 2011
Real-time
multi-scale TV image analysis on DSP, with application to image metrics, and
control of image enhancement functions
With NXP
61.
Marc Brouns, EE, 2010
Implementation of SIMD architecture on
FPGA
62.
Rick Boer, ES, 2010
Interactive Free Viewpoint 3D TV
Rendering Platform
With Silicon Hive
63.
Atilla Filiz, ES, 2010
Analyzing the Feasibility of Real-Time
Dense Stereo on a Dual DSP setup
64. Maurice Peemen, EE, 2010
Mapping Convolutional Neural Networks on
a Reconfigurable FPGA Platform
65.
Qiao Peng, EE, 2010
Design and Optimization of Digital
Hearing Aid System Based on Silicon Hive Technology
With Silicon Hive
66.
Joost Hausmans, ES, 2010
Resynchronization of Dataflow Graphs
With NXP
67.
Stefan Geuns, ES, 2010
Parallelization of While-Loops in Nested
Loop Programs for Real-time Multiprocessor Systems
With NXP
68.
Zhenghie Lu, EE, 2010
MPSoC Platform Design and Simulation for
Power Performance Estimation
With STEricsson
69.
Corne Kraaij, EE, 2010
Exploring Loop Buffers for SIMD
Architectures
70.
Michiel Rooijakkers, EE, 2010
Design space exploration for scalable
R-peak detection; Trading quality versus power
With Philips Research
71.
Wouter van der Put, ES, 2010
Time-predictability of a computer system
With Prodrive
72.
Wouter van Heijningen, EE
Testing mechatronic embedded control
HW/SW using simulation and fault injection
With OCE
73.
Robert van Vooren, EE, 2009
Observation for resource-constrained
devices
74. Bart van Stiphout, EE, 2009
Best view selection using multiple smart
cameras
75.
Gert-Jan van den Braak, EE, 2009
Compile-time GPU Memory Access
Optimizations
76.
Xicai Chen, EE, 2009
Design Space Exploration for Hough
Transform Mappedto VLIW Architecture
Exploring Subword Parallelism
With Silicon Hive
77.
Roel Jordans, EE, 2009
Integration of observation into products:
a case study with the Android platform
78.
Jochem van der Meer, EE, 2009
Analysis and design-space
exploration of a dynamic interconnect for SIMD architectures
79.
Cedric Nugteren, ES, 2009
Improving CUDA’s Compiler through the
Visualization of Decoded GPU Binaries
80.
She Dongrui, ES, 2009
FPGA Platform for Emulation of Composable
and Predictable MPSoC Power Management
81.
Firew Siyoum, ES, 2009
TLM-based Multi-core System Level
Modeling and Simulation (TM2S)
With Recore
82. Willisont Hayes, ES, 2009
Memory Pattern Generation based on
Specification and Environment
83.
Zhenyu Ye, ES, 2009
Architecture Exploration for Parallel
Processing Systems
84.
Julian Pallares Garcia, Erasmus
Valencia, 2009
POOSL on Transputers
Erasmus student
85.
Haibin Wang, ES, 2009
Modeling and Performance Analysis for Light Control
Subsystem
With ASML
86.
Frank Ophelders, ES, 2009
A Tuneable Software Cache Coherence
Protocol for Heterogeneous MPSoCs
With NXP
87.
Andrew Thomas Nelson, ES, 2009
Conservative Application-Level
Performance Analysis through Simulation of a Multiprocessor System on Chip
88.
Rolf van de Burgt, EE, 2008
Atalanta Wingman: Blimp positioning in a
wireless sensor network
With DEVLAB
89.
Thom Gielen, EE, 2008
Extracting SDF from sequential
applications for MPSoC and implementation on FPGA
With NUS Singapore
90.
Alberto Falcon Garcia, Erasmus Las
Palmas, 2008
Erasmus student
91.
Michael Koch, EE, 2008
Distributed smart camera calibration
using LED
With NXP
92.
Paul Meys, EE, 2008
Mapping a YUV to RGB application onto
Cell Broadband Engine and Nvidia Geforce 8
93.
Onno Brunklaus, EE, 2008
Implementing a scan-to-printer image
chain on a massive parallel SIMD processor
With OCE
94.
Yifan He, EE, 2008
Real-Time Hough Transform on 1-D SIMD
Processors: Implementation and Architecture Exploration
With NXP
95.
Andre Boon, EE, 2008
A Hybrid Processor Architecture for
(Ir)regular Image Processing on an FPGA
With Prodrive
96.
Roy Phillipsen, EE, 2008
PIR Model Driven Engineering
With ASML
97.
Bert van Moll, EE, 2008
Fast and Accurate Protocol Specific Bus
Modeling using TLM 2.0
With NXP
98.
Win King Wan, ES, 2008
Evaluation and desing of multi-processor
architectures
99.
Tim Drijvers, ES, 2008
Fast Huffman Decoding by Exploiting Data
level Parallelism
With Silicon Hive
100.
Abhiram Ganesh, Exhange student Munipal,
India, 2008
Gesture analysis and mapping to Xetal
like platforms
101.
Raymond Frijns, 2008
DC-SIMD : Dynamic Communication for SIMD
processors
102.
Daan Alberga, 2008
An implementation of Reactive Process
Networks
103.
Rogier Thus, 2007
Generation of Models Based on Modelling
Patterns
104.
Mark Sleegers, 2007
Prototyping of Dynamic Reconfiguration in
a NoC based System on Chip
With Silicon Hive
105.
Tijs Versteegde, 2007
Development of Sesia: a VLIW Processor
for Multi-Standard Turbo Decoding
With Silicon Hive
106.
Teresa Median, Erasmus, Las Palmas, 2006
Fast modelling and analysis of NoC-based
MPSoCs
Erasmus student
107.
Dai Rui, TU/e-NUS joined master, 2005
Real time clustering and visualization of
dynamic information using a massively parallel embedded processor
With OCE
108.
Michiel Oostindie, 2005
Exploring boundaries in game processing
109.
Veena Parashuram, 2005
Mapping object detection onto a
heterogeneous multiprocessor vision platform
With Philips
110.
Isabel Marquez, Erasmus, Las Palmas,
2005
Hardware Communication Services for Synchronous Data Flow in the Mini-NoC
Erasmus student
111.
Jose C. Prats Ortiz, Erasmus, Las
Palmas, 2005
Design of components for a NoC-based
MPSoC Platform; Adding a shared memory
node to the mNoC
Erasmus student
112.
Jos Hulzink, 2004
Optimization of Ultra Long Instruction
Word processors for the Software Defined Radio (SDR) domain
With Silicon Hive
113.
Tycho van Meeuwen, EE, 2002
Data-cache conflict-miss reduction by
high-level data-layout transformations
With IMEC Leuven
Period: Febr 1986-August 2001