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Education |
- 2005-present:
Ph.D. Candidate,
Electrical Engineering,
National University of Singapore (NUS), Singapore
Technische Universiteit Eindhoven (TU/e), The Netherlands
- 2000-2004:
B.S.,
Dept. of Electrical Engineering,
Zhejiang University (ZJU), P.R.China |
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Research Interests |
- Electronics design automation (with emphasis on design for manufacturability (DFM)
for nanometer IC technologies and SoC integration)
- (Ultra) Low-power and robust digital circuits design
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Project On-The-Go |
Exploring solutions for ultra low-power applications, such as wireless motes, in-vivo biomedical implants and instrumentation, ambient intelligent devices, etc. is becoming increasingly important. In contrast to analog circuit design where lowering the supply voltage to the sub-threshold region is generally avoided because of the small values of the drive currents and of the exceedingly large noise,
CMOS digital logic gates can work seamlessly from full VDD to well below threshold voltage. Operating CMOS digital circuits in the sub-threshold region is a promising solution for ultra-low energy applications. However, simply reducing supply voltage below sub-threshold causes significant robustness problem due to exponentially diminished drive current. This robustness problem gets even worse in presence of ever-increasing process variations.
In this project, we will explore the feasibility for digital logics to work safely in the sub-threshold region. Both transistor level optimization and architectural level optimization methodologies towards a better robustness and higher energy efficiency will be covered.
Partners Involved:
- Technische Universiteit Eindhoven (TU/e)
- National University of Singapore (NUS)
- NXP Research (Former Philips Semiconductors)
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Links |
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Last Update: March 10, 2007
© Pu Yu, 2007
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PU YU (ÆÑÓî) | Ph.D. Candidate
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