PhD Project Vincent Nollet

Vincent Nollet

PhD Project: Centralized Run-Time Resource Management for Future MPSoC Platforms

1. Introduction

Future System-on-Chip (SoC) platforms will contain a mixture of heterogeneous processing elements (PEs), also denoted as tiles. These programmable tiles will be interconnected by a configurable on-chip communications fabric or a Network-on-Chip (NoC). Dynamically (i.e. at run-time) managing the computation and communication resources of such a platform is a challenging task, especially when the platform contains special PE types such as fine-grain reconfigurable hardware (i.e. FPGA fabric).

In addition, there is also a challenge in defining/handling the interface between the run-time management layer and the application layer. In order to be efficient, there should be a close interaction (cooperation) between application and run-time management layer. In addition, by using design-time application exploration information and by adding application-specific run-time managment functionality into the application, run-time resource management should prove to be more efficient.

This PhD project actually contains two parts. The first part mainly considers management of the platform resources (i.e. computation and communication resources) when the available application information is very limited, while the second part focuses on the use of extensive design-time application exploration information to improve run-time decision making.

2. PART I: Run-Time Management of MPSoC Communication and Computation Resources

The first part of this PhD considers a heterogeneous multiprocessor platform that contains fine-grain reconfigurable hardware tiles interconnected by a best-effort Network-on-Chip.
The (centralized) run-time resource manager is responsible for allocating the right amount of communication and computation resources to accomodate the communicating tasks of an incoming application. This basically boils down to (1) allocating computation resources, while taking the specific properties of the FPGA fabric tiles into account, (2) managing communication resources in a best-effort NoC (by using an injection-rate control mechanism) and (3) handling the various run-time task migration issues in a Network-on-Chip environment.

Publications PART I:

J-Y. Mignolet, V. Nollet, P. Coene, D.Verkest, S. Vernalde, R. Lauwereins, "Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip", Proceedings of Design, Automation and Test in Europe (DATE) Conference, pp. 986-991, Munich, Germany, March 2003.
V. Nollet, P. Coene, D. Verkest, S. Vernalde, R. Lauwereins , "Designing an Operating System for a Heterogeneous Reconfigurable SoC", Proceedings of the Reconfigurable Architectures Workshop (RAW), Nice, France, April 2003
V. Nollet, J-Y Mignolet, T.D. Bartic, D. Verkest, S. Vernalde, R. Lauwereins , "Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems", Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp 81-87, Las Vegas, Nevada, USA, June 2003.
T.A. Bartic, J-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, R. Lauwereins, "Highly Scalable Network on Chip for Reconfigurable Systems", Systems on Chip Conference (SOC 2003), Tampere, Finland, November 2003.
V. Nollet, T. Marescaux, D. Verkest, J-Y. Mignolet, S. Vernalde, "Operating System controlled Network-on-Chip", Proceedings of Design Automation Conference (DAC), pp. 256-259, San Diego, June 2004, ISBN 1-58113-916-0.
J-Y. Mignolet, V. Nollet, P. Coene, D. Verkest, S. Vernalde, R. Lauwereins, "Enabling Run-time Task Relocation on Reconfigurable Systems", "New Algorithms, Architectures and Applications for Reconfigurable Computing", Lysaght, Patrick; Rosenstiel, Wolfgang (Eds.), 2005, ISBN: 1-4020-3127-0, © Springer-Verlag.
T. Marescaux, V. Nollet, J-Y. Mignolet, A. Bartic, W. Moffat, P. Avasare, P.Coene, D. Verkest, S. Vernalde, R. Lauwereins, "Run-Time Support for Heterogeneous Multitasking on Reconfigurable SoCs" , Integration - the VLSI journal, special edition.
T. A. Bartic, J-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, R. Lauwereins, "Topology Adaptive Network-on-Chip Design and Implementation" , IEE Proc. Computers and Digital Techniques. (accepted)
G. Talavera, V. Nollet, J-Y Mignolet, D. Verkest, S. Vernalde, R. Lauwereins, J. Carrabina, "Hardware-Software Debugging Techniques for Reconfigurable Systems on Chip" , IEEE International Conference on Industrial Technology (ICIT 2004).
V. Nollet, P. Avasare, J-Y. Mignolet, D. Verkest, "Low Cost Task Migration Initiation in a Heterogeneous MP-SoC" , Proceedings of Design, Automation and Test in Europe Conference (DATE), pp 234-239, Munich, Germany, March 2005.
V. Nollet, T. Marescaux, P. Avasare, J-Y. Mignolet, D. Verkest, "Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles" , Proceedings of Design, Automation and Test in Europe (DATE) Conference, pp 252-253, Munich, Germany, March 2005.
P. Avasare, V. Nollet, J-Y. Mignolet, D. Verkest ,"Centralized End-to-End Flow Control in a Best-Effort Network-on-Chip", Proceedings of the ACM Conference on Embedded Software (EMSOFT). (accepted)

3. PART II: Pareto-Based Application-Aware Run-Time Resource Management

The second part of this PhD considers the effect of the availability of extensive design-time application exploration information on run-time management. This means that for every application there is a Pareto surface defined by multiple Pareto points that each represent a trade-off between application cost (e.g. energy consumption), application constraints (e.g. execution time) and platform resource usage (e.g. computation, communication and memory resources).
In this case, the main job of the run-time resource manager is to choose a Pareto (operating) point that minimizes the cost, while taking the (user) constraints and the status of the platform into account. After choosing the most appropriate Pareto point, the resource assignment algorithm still needs to determine which platform resources will need to be allocated.

The main issues in this part of the PhD is determining the influence of the amount of Pareto axis, the amount of Pareto points and the shape of the curve on the Pareto point selection algorithm. To this end, it is important to be able to generate realistic Pareto surfaces of an application in a fast way. In addition, one has to investigate the interaction between Pareto point selection algorithm and the resource assignment algorithm. Finally, one also needs to determine the relevant run-time/design-time parameters that influence Pareto point switching and to come up with a (generic) mechanism to perform run-time Pareto switching. Run-time Pareto point switching involves e.g. changing the parallelisation of the application at run-time (i.e. going from one Pareto point to another Pareto point).

Publications PART II:

Ch. Ykman-Couvreur, E. Brockmeyer, V. Nollet, T. Marescaux, F. Catthoor, H. Corporaal, "Design-Time Application Exploration for MP-SoC Customized Run-Time Management", Systems on Chip Conference (SOC 2005). (submitted)