A partially connected architecture is a VLIW architecture in which some (many) of the internal connections have been removed in order to reduce their negative effect on the performance and costs. It is however commonly assumed that code generation for such architectures is prohibitively difficult.
The goal of this project is to show that a more efficient hardware design is indeed a feasible option. The main focus is on the back-end of the compiler: the scheduling stage. For the code generation for hardware efficient VLIW's, it is necessary that the scheduler can deal with the restrictions imposed by the limited connectivity.
The final goal is to design a scheduling method that can deal with arbitrarily
connected VLIW's, and to prove that the method works and has a competitive
performance. When this goal has been achieved, it will be possible to design
a class of processor architectures that is far more efficient in hardware
and therefore gives a better performance than the current generation VLIW's.
This method has been implemented in a scheduler. Given a machine description (in a file), the scheduler can schedule single basic blocks with a reasonable performance. Due to the generality of the method, the scheduler can handle almost any possible architecture.
Currently we are extending this scheduler to allow it to schedule across
multiple basic blocks. We are also working on smart placement algorithms
for the first stage,
Henk Corporaal - Eindhoven
University
Thesis advisor