Electronic Systems HJHJHJHJHJHJHJHJHJHJHJHJTU/e

Book Chapters

  1. H. Jiao and V. Kursun, “Tri-Mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits,” VLSI-SoC: Forward-Looking Trends in IC and System Design, J. L. Ayala, D. A. Atienza, and R. Reis, (Eds.), Springer, pp. 258 - 290, 2012, ISBN 978-3-642-28565-3.

Journal Publications

  1. H. Jiao, Y. Qiu, and V. Kursun, "Variability-Aware 7T SRAM Circuit with Low Leakage High Data Stability SLEEP Mode," Elsevier Integration, the VLSI Journal, Vol. 53, pp. 68-79, March 2016.
  2. H. Jiao, Y. Qiu, and V. Kursun, "Low Power and Robust Memory Circuits with Asymmetrical Ground Gating," Elsevier Microelectronics Journal, Vol. 48, pp. 109-119, February 2016.
  3. S. M. Salahuddin, H. Jiao, and V. Kursun, “FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability,” Transactions on Electrical and Electronic Materials, Vol. 16, No. 6, pp. 293-302, December 2015.
  4. Y. Sun, H. Jiao, and V. Kursun, “A Novel Robust and Low-Leakage SRAM Cell with Nine Carbon Nanotube Transistors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 9, pp. 1729-1739, September 2015.
  5. H. Jiao and V. Kursun, “Mode Transition Timing and Energy Overhead Analysis in Noise-Aware MTCMOS Circuits,” Elsevier Microelectronics Journal, Vol. 45, No. 8, pp. 1125-1131, August 2014.
  6. H. Jiao and V. Kursun, “Reactivation Noise Suppression with Sleep Signal Slew Rate Modulation in MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 3, pp. 533-545, March 2013.
  7. H. Jiao and V. Kursun, “Threshold Voltage Tuning for Faster Activation with Lower Noise in Tri-Mode MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 4, pp. 741-745, April 2012.
  8. H. Jiao and V. Kursun, “Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 5, pp. 763-773, May 2011.
  9. H. Jiao and V. Kursun, “Noise-Aware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias,” World Scientific Journal of Circuits, Systems, and Computers (Special Issue on Green Integrated Circuits and Systems, INVITED PAPER), Vol. 20, No. 1, pp. 125-145, February 2011.
  10. H. Jiao and V. Kursun, “Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits,” IEEE Transactions on Circuits and Systems I, Vol. 57, No. 8, pp. 2053-2065, August 2010.
  11. H. Jiao and V. Kursun, “Low-Leakage and Compact Registers with Easy-Sleep Mode,” ASP Journal of Low Power Electronics, Vol. 6, No. 2, pp. 263-279, August 2010.
  12. H. Jiao, L. Chen, Z. Li, Q. Yang, and T. Ye, “OPC Reuse Based on A Reduced Standard Cell Library,” IOPscience Journal of Semiconductors, Vol. 29, No. 5, pp. 1016-1021, May 2008.

Conference Publications

  1. H. Jiao, Y. Qiu, and V. Kursun, “Variations-Tolerant 9T SRAM Circuit with Robust and Low Leakage SLEEP Mode,” Proceedings of the IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), July 2016.
  2. E. J. Marinissen, T. McLaurin, and H. Jiao, “IEEE Std P1838: DfT Standard-under-Development for 2.5D-, 3D-, and 5.5D-SICs,” Proceedings of the IEEE European Test Symposium (ETS), May 2016.
  3. S. Hamdioui, L. Xie, H. A. Du Nguyen, M. Taouil, K. Bertels, H. Corporaal, H. Jiao, F. Catthoor, D. Wouters, L. Eike, and J. van Lunteren, “Memristor Based Computation-in-Memory Architecture for Data-Intensive Applications,” Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe, pp. 1718-1725, March 2015.
  4. Y. Sun, H. Jiao, and V. Kursun, “Low-Leakage 9-CN-MOSFET SRAM Cell with Enhanced Read and Write Voltage Margins,” Proceedings of the IEEE International Conference on Microelectronics, pp. 164-167, December 2014 (Best Paper Award).
  5. H. Jiao and V. Kursun, “Novel High Electrical Quality Seven-Transistor Memory Cell with Asymmetrical Ground Gating,” Proceedings of the IEEE International SoC Design Conference, pp. 255-258, November 2013.
  6. H. Jiao and V. Kursun, “Characterization of Mode Transition Timing Overhead for Net Energy Savings in Low-Noise MTCMOS Circuits,” Proceedings of the IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 150-155, October 2013.
  7. H. Jiao and V. Kursun, “Ground Gated 8T SRAM Cells with Enhanced Read and Hold Data Stability,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 52-57, August 2013.
  8. S. M. Salahuddin, H. Jiao, and V. Kursun, “Characterization of FinFET SRAM Cells with Asymmetrically Gate Underlapped Bitline Access Transistors under Process Parameter Fluctuations,” Proceedings of the IEEE International Conference on Electron Devices and Solid-State Circuits, June 2013.
  9. S. M. Salahuddin, H. Jiao, and V. Kursun, “Low-Leakage Hybrid FinFET SRAM Cell with Asymmetrical Gate Overlap / Underlap Bitline Access Transistors for Enhanced Read Data Stability,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2331-2334, May 2013.
  10. S. M. Salahuddin, H. Jiao, and V. Kursun, “A Novel 6T SRAM Cell with Asymmetrically Gate Underlap Engineered FinFETs for Enhanced Read Data Stability and Write Ability,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, pp. 353-358, March 2013.
  11. H. Jiao and V. Kursun, “Characterization of Noise-Aware MTCMOS Circuits with Sleep Signal Slew Rate Modulation under Process Parameter Variations,” Proceedings of the IEEE International Conference on Electronics, Information, and Communication, January 2013.
  12. H. Jiao and V. Kursun, “Multi-Phase Sleep Signal Modulation for Mode Transition Noise Mitigation in MTCMOS Circuits,” Proceedings of the IEEE International SoC Design Conference, pp. 466-469, November 2012 (SoC Design Group Award).
  13. H. Jiao and V. Kursun, “Low Power and Robust Ground Gated Memory Banks with Combined Write Assist Techniques,” Proceedings of the IEEE Faible Tension Faible Consommation (FTFC), June 2012.
  14. H. Jiao and V. Kursun, “Full-Custom Design of Low Leakage Data Preserving Ground Gated 6T SRAM Cells to Facilitate Single-Ended Write Operations,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 484-487, May 2012.
  15. H. Jiao and V. Kursun, “Sleep Signal Slew Rate Modulation for Mode Transition Noise Suppression in Ground Gated Integrated Circuits,” Proceedings of the IEEE International SoC Conference, pp. 365-370, September 2011.
  16. H. Jiao and V. Kursun, “Asymmetrical Ground Gating for Low Leakage and Data Robust Sleep Mode in Memory Banks,” Proceedings of the IEEE International Symposium on VLSI Design, Automation and Test, pp. 205-208, April 2011.
  17. H. Jiao and V. Kursun, “Power Gated SRAM Circuits with Data Retention Capability and High Immunity to Noise: A Comparison for Reliability in Low Leakage Sleep Mode,” Proceedings of the IEEE International SoC Design Conference, pp. 5-8, November 2010 (INVITED PAPER).
  18. H. Jiao and V. Kursun, “How Forward Body Bias Helps to Reduce Ground Bouncing Noise and Silicon Area in MTCMOS Circuits: Divulging the Basic Mechanism,” Proceedings of the IEEE International SoC Design Conference, pp. 9-12, November 2010 (INVITED PAPER).
  19. H. Jiao and V. Kursun, “Reactivation Noise Suppression with Threshold Voltage Tuning in Sequential MTCMOS Circuits,” Proceedings of the IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 347-351, September 2010.
  20. H. Jiao and V. Kursun, “High-Speed and Low-Leakage MTCMOS Memory Registers,” Proceedings of the IEEE/ACM Asia Symposium on Quality Electronic Design, pp. 17-22, August 2010.
  21. H. Jiao and V. Kursun, “Dynamic Forward Body Bias Enhanced Tri-Mode MTCMOS,” Proceedings of the IEEE/ACM Asia Symposium on Quality Electronic Design, pp. 33-37, August 2010.
  22. H. Jiao and V. Kursun, “Smooth Awakenings: Reactivation Noise Suppressed Low-Leakage and Robust MTCMOS Flip-Flops,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3845-3848, May 2010.
  23. H. Jiao and V. Kursun, “Ground Bouncing Noise Aware Sequential MTCMOS Circuits with Data Retention Capability,” Proceedings of the IEEE International Symposium on Integrated Circuits, pp. 534-537, December 2009 (INVITED PAPER).
  24. H. Jiao and V. Kursun, “Sleep Transistor Forward Body Bias: An Extra Knob to Lower Ground Bouncing Noise in MTCMOS Circuits,” Proceedings of the IEEE International SoC Design Conference, pp. 216-219, November 2009 (INVITED PAPER).
  25. H. Jiao and V. Kursun, “Ground Bouncing Noise Suppression Techniques for MTCMOS Circuits,” Proceedings of the IEEE/ACM Asia Symposium on Quality Electronic Design, pp. 64-70, July 2009.
  26. H. Jiao and L. Chen, “Cellwise OPC Based on Reduced Standard Cell Library,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design, pp. 810-814, March 2008.

Patents

  1. V. Kursun, H. Zhu, and H. Jiao, “Static Random Access Memory and Method for Controlling the Same,” Chinese Patent, CN102467961A, October 8, 2014.
  2. V. Kursun, S. M. Salahuddin, and H. Jiao, “SRAM with Asymmetrical Transistors and Method for Controlling the Same,” Chinese Patent, CN103489914A, January 1, 2014.

Invited Talks

  1. "Nanoscale Digital IC Design — Low Power Paradigms", Peking University, Shenzhen Graduate School, Shenzhen, China, Nov. 5, 2015.
  2. "Noise Mitigation in Low Leakage MTCMOS Circuits", CWTe (Center for Wireless Technology Eindhoven) Colloquium, Eindhoven University of Technology, Eindhoven, The Netherlands, March 30, 2015.
  3. "Energy-Efficient and Variations-Resilient Nanoscale Integrated Circuits", imec, Leuven, Begium, October 16, 2013.
  4. "Energy-Efficient and Variations-Resilient Nanoscale Integrated Circuits", Eindhoven University of Technology, Eindhoven, The Netherlands, June 10, 2013.

Thesis

  • Doctoral Thesis
  • Noise Mitigation in Low Leakage MTCMOS Circuits

    Supervisor: Prof. Volkan Kursun

    The Hong Kong University of Science and Technology, Hong Kong

  • Master Thesis
  • Research on OPC Reuse Based on Reduced Standard Cell Library

    Supervisor: Prof. Tianchun Ye and Prof. Lan Chen

    Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China

  • Bachelor Thesis
  • Mixed-signal Circuit System Based on CPLD and MCU

    Supervisor: Prof. Wei Jiang

    Shandong University, Shandong, China