Publications

  1. M. V. Leussen, J. Huisken, L. Wang, H. Jiao, and J. P. de Gyvez, “Reconfigurable Support Vector Machine Classifier with Approximate Computing,” in 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, vol. 3, pp. 13–18. [Abstract] [BibTeX] [ CrossRef] Support Vector Machine (SVM) is one of the most popular machine learning algorithms. An energy-efficient SVM classifier is proposed in this paper, where approximate computing is utilized to reduce energy consumption and silicon area. A hardware architecture with reconfigurable kernels and overflow-resilient limiter is presented. For different applications, different kernels can be chosen and configured to achieve the optimum energy efficiency while achieving the performance requirement. For an epileptic seizure detection application, on average, 15% energy and 14% area savings are achieved with the proposed approximate SVM classifier compared to a fully-accurate SVM implementation with almost no accuracy degradation.
    @inproceedings{Leussen2017SVM,
      author = {Leussen, Martin Van and Huisken, Jos and Wang, Lei and Jiao, Hailong and de Gyvez, Jos{\'e} Pineda},
      booktitle = {2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
      title = {Reconfigurable Support Vector Machine Classifier with Approximate Computing},
      year = {2017},
      volume = {3},
      number = {},
      pages = {13-18},
      keywords = {energy conservation;pattern classification;support vector machines;SVM;approximate computing;energy consumption reduction;energy-efficient SVM classifier;hardware architecture;machine learning algorithms;overflow-resilient limiter;reconfigurable kernels;reconfigurable support vector machine classifier;silicon area reduction;Approximate computing;Computer architecture;Hardware;Kernel;Support vector machine classification;Training;Machine learning;approximate multiplier;energy efficiency;reconfigurable architecture},
      doi = {10.1109/ISVLSI.2017.13},
      issn = {},
      month = jul,
      url = {http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7961326},
      organization = {IEEE}
    }
    
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  2. H. Kim et al., “A Configurable and Low-Power Mixed Signal SoC for Portable ECG Monitoring Applications,” IEEE Transactions on Biomedical Circuits and Systems, vol. 8, no. 2, pp. 257–267, Apr. 2014. [Abstract] [BibTeX] [ CrossRef] This paper describes a mixed-signal ECG System-on-chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel impedance measurement with high signal quality. A custom digital signal processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. The SoC is implemented in 0.18 #x03BC;m CMOS process and consumes minimum 31.1 #x03BC;W from a 1.2V.
    @article{Kim2014a,
      author = {Kim, Hyejung and Kim, Sunyoung and {Van Helleputte}, Nick and Artes, Antonio and Konijnenburg, Mario and Huisken, Jos and Yazicioglu, Refet Firat and {Van Hoof}, Chris},
      doi = {10.1109/TBCAS.2013.2260159},
      file = {:C$\backslash$:/Users/huisken/AppData/Local/Mendeley Ltd./Mendeley Desktop/Downloaded/QSHI7GRM/Kim et al. - 2013 - A Configurable and Low-Power Mixed Signal SoC for .html:html},
      isbn = {978-4-86348-166-4},
      issn = {19324545},
      journal = {IEEE Transactions on Biomedical Circuits and Systems},
      keywords = {Artifacts,Biopotential recording,CMOS integrated circuits,CMOS process,Computer-Assisted,Computer-Assisted: instrumentat,ECG,Electrocardiography,Electrocardiography: instrumentation,Electrocardiography: methods,Equipment Design,Lab-On-A-Chip Devices,R peak detection,Signal Processing,System-on-Chip (SoC),analog front-end,biomedical electronics,configurable functionality,digital signal processing chips,digital signal processor,electric impedance,electrocardiography,low-power electronics,low-power mixed signal SoC,medical signal processing,mixed analogue-digital integrated circuits,motion artifact reduction,motion artifact removal,patient monitoring,portable ECG monitoring applications,power 31.1 muW,single channel impedance measurement,size 0.18 mum,voltage 1.2 V},
      mendeley-tags = {Biopotential recording,CMOS integrated circuits,CMOS process,ECG,R peak detection,System-on-Chip (SoC),analog front-end,biomedical electronics,configurable functionality,digital signal processing chips,digital signal processor,electric impedance,electrocardiography,low-power electronics,low-power mixed signal SoC,medical signal processing,mixed analogue-digital integrated circuits,motion artifact reduction,motion artifact removal,patient monitoring,portable ECG monitoring applications,power 31.1 muW,single channel impedance measurement,size 0.18 mum,voltage 1.2 V},
      month = apr,
      number = {2},
      pages = {257--267},
      pmid = {24875285},
      shorttitle = {Biomedical Circuits and Systems, IEEE Transactions},
      title = {{A Configurable and Low-Power Mixed Signal SoC for Portable ECG Monitoring Applications}},
      volume = {8},
      year = {2014}
    }
    
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  3. M. Konijnenburg et al., “Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, 2013, pp. 430–431. [Abstract] [BibTeX] [ CrossRef] Wireless Sensor Nodes (WSN) have a wide range of applications in health care and life style monitoring. Their severe energy constraint is often addressed through minimizing the amount of transmitted data by way of energy-efficient on-node signal processing. The rationale for this approach is that a large portion of WSN energy is consumed by the radio communication even for very low-data-rate situations [1]. Efficient on-node processing has been the subject of recent work, with the common element being aggressive voltage scaling into the sub-threshold region [2–4]. A major assumption of the existing works is that the amount of required computation is low, justifying an on-node processor with limited computational capability. While this might be the case for many applications of WSNs, emerging ambulatory biomedical signal processing applications exceed the performance offered by today’s on-node processors.
    @inproceedings{konijnenburg_reliable_2013,
      title = {Reliable and energy-efficient {1MHz} {0.4V} dynamically reconfigurable {SoC} for {ExG} applications in 40nm {LP} {CMOS}},
      doi = {10.1109/ISSCC.2013.6487801},
      booktitle = {Solid-State Circuits Conference Digest of Technical Papers ({ISSCC)}, 2013 {IEEE} International},
      author = {Konijnenburg, Mario and Cho, Yeongojn and Ashouei, Maryam and Gemmeke, Tobias and Kim, Changmoo and Hulzink, Jos and Stuyt, Jan and Jung, Mookyung and Huisken, Jos and Ryu, Soojung and Kim, Jungwook and Groot, Harmke de},
      year = {2013},
      pages = {430--431},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\EPRNQNXF\articleDetails.html:text/html}
    }
    
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  4. V. Sharma, S. Cosemans, M. Ashouei, J. Huisken, F. Catthoor, and W. Dehaene, “Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM,” in Design, Automation Test in Europe Conference Exhibition (DATE), 2012, 2012, pp. 1042–1047. [Abstract] [BibTeX] This paper presents litho friendly circuit techniques for variability resilient low power 8T SRAM. The new local assist circuitry achieves a state-of-the-art low energy and variability resilient WRITE operation and improves the degraded access speed of SRAM cells at low voltages. Differential VSS bias increases the variability resilience. The physical regularity in the layout of local assist circuitry enables litho optimization thereby reducing the area overhead associated with existing local assist techniques. Statistical simulations in 40nm LP CMOS technology reveals 10x reduction in WRITE energy consumption, 10^\textrm3x reduction in write failures, 6.5x improvement in read access time and 31% reduction in the area overhead.
    @inproceedings{sharma_ultra_2012-1,
      title = {Ultra low power litho friendly local assist circuitry for variability resilient {8T} {SRAM}},
      booktitle = {Design, Automation Test in Europe Conference Exhibition {(DATE)}, 2012},
      author = {Sharma, V. and Cosemans, S. and Ashouei, M. and Huisken, J. and Catthoor, F. and Dehaene, W.},
      month = mar,
      year = {2012},
      keywords = {area overhead, {CMOS} memory circuits, failure analysis, Integrated circuit reliability, low-power electronics, {LP} {CMOS} technology, photolithography, size 40 nm, {SRAM} chips, statistical analysis, statistical simulations, ultralow power lithography friendly local assist circuitry, variability resilient {8T} {SRAM}, variability resilient {WRITE} operation, write failures},
      pages = {1042 --1047},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\Z2ZQVQ6X\articleDetails.html:text/html}
    }
    
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  5. G. Psychou, R. Fasthuber, F. Catthoor, J. Hulzink, and J. Huisken, “Sub-word handling in data-parallel mapping,” in ARCS Workshops (ARCS), 2012, 2012, pp. 1–7. [Abstract] [BibTeX] Data-parallel processing is a widely applicable technique, which can be implemented on different processor styles, with varying capabilities. Here we address single or multi-core data-parallel instruction-set processors. Often, handling and reorganisation of the parallel data may be needed because of diverse needs during the execution of the application code. Signal word-length considerations are crucial to incorporate because they influence the outcome very strongly. This paper focuses on the broader solution space of selecting sub-word lengths (at design time) including especially hybrids, so that mapping on these data parallel single/multi-core processors is more energy-efficient. Our goal is to introduce systematic exploration techniques so that part of the designers effort is removed. The methodology is evaluated on a representative application driver for a number of data-path variants and the most promising trade-off points are indicated. The range of throughput-energy ratios among the different mapping implementations is spanning a factor of 2.2.
    @inproceedings{psychou_sub-word_2012,
      title = {Sub-word handling in data-parallel mapping},
      booktitle = {{ARCS} Workshops {(ARCS)}, 2012},
      author = {Psychou, G. and Fasthuber, R. and Catthoor, F. and Hulzink, J. and Huisken, J.},
      month = feb,
      year = {2012},
      keywords = {data handling, data parallel mapping, data parallel processing, instruction sets, multicore data-parallel instruction-set processors, multiprocessing systems, parallel data reorganisation, parallel processing, power aware computing, representative application driver, signal word-length, single-core data-parallel instruction-set processors, subword handling, subword length selection, systematic exploration techniques, throughput-energy ratios, trade-off points},
      pages = {1 --7},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\CPGEN3G7\articleDetails.html:text/html}
    }
    
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  6. V. Sharma, S. Cosemans, M. Ashouie, J. Huisken, F. Catthoor, and W. Dehaene, “Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors,” IEEE Micro, vol. 32, no. 5, pp. 10–24, Oct. 2012. [Abstract] [BibTeX] [ CrossRef] Medical diagnosis and healthcare are at the onset of a revolution fueled by improvements in smart sensors and body area networks. Those sensor nodes’ computation and memory requirements are growing, but their energy resources do not increase; thus, more energy-efficient memories and processors are required. New circuit-design techniques that drastically reduce the static RAM (SRAM) memories’ energy consumption while still achieving tens of megahertz of operation are discussed.
    @article{sharma_ultra_2012,
      title = {Ultra Low-Energy {SRAM} Design for Smart Ubiquitous Sensors},
      volume = {32},
      issn = {0272-1732},
      doi = {10.1109/MM.2012.58},
      number = {5},
      journal = {{IEEE} Micro},
      author = {Sharma, Vibhu and Cosemans, Stefan and Ashouie, Maryam and Huisken, Jos and Catthoor, Francky and Dehaene, Wim},
      month = oct,
      year = {2012},
      pages = {10 --24},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\ZECDWRB6\articleDetails.html:text/html}
    }
    
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  7. B. Liu, M. Ashouei, J. Huisken, and J. P. de Gyvez, “Standard cell sizing for subthreshold operation,” in 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC), 2012, pp. 962–967. [Abstract] [BibTeX] Process variability severely impacts the performance of circuits operating in the subthreshold domain. Among other reasons, this mainly stems from the fact that subthreshold current follows a widely spread Log-Normal distribution. In this paper we introduce a new transistor sizing methodology for standard cells. Our premise relies on balancing the N and P network currents based on statistical formulations. Our approach renders more robust cells. We observe up to 57% better performance and 69% lower energy consumption on a set of ISCAS circuits when they are synthesized with our library as opposed to a commercial library in a CMOS 90nm technology.
    @inproceedings{liu_standard_2012,
      title = {Standard cell sizing for subthreshold operation},
      booktitle = {2012 49th {ACM/EDAC/IEEE} Design Automation Conference {(DAC)}},
      author = {Liu, Bo and Ashouei, M. and Huisken, J. and de Gyvez, {J.P.}},
      month = jun,
      year = {2012},
      keywords = {cellular arrays, circuit performance, {CMOS} integrated circuits, {CMOS} technology, electronic engineering computing, {ISCAS} circuits, log normal distribution, log-normal distribution, process variability, standard cell sizing, subthreshold operation, transistor circuits, transistor sizing},
      pages = {962 --967},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\IUW9T7PX\articleDetails.html:text/html}
    }
    
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  8. V. Sharma, S. Cosemans, M. Ashouei, J. Huisken, F. Catthoor, and W. Dehaene, “A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy,” IEEE Journal of Solid-State Circuits, vol. 46, no. 10, pp. 2416–2430, Oct. 2011. [Abstract] [BibTeX] [ CrossRef] An ultra low energy, 128 kbit 6T SRAM in 90 nm LP CMOS with energy consumption of 4.4 pJ/access, operating at 80 MHz for the wireless sensor applications is developed. The variability resilient and low power techniques developed include innovation in the local architecture with the use of local read/write assist circuitry. The energy-efficient hierarchical bit-lines structure includes low swing global bit-lines and VDD/2 pre-charged short local bit-lines. The innovative Multi-Sized SA redundancy (MS-SA-R) calibration technique for the global read sense amplifiers of the SRAM not only adds to the variability resilience but also yields maximum energy reduction compared with existing calibration techniques.
    @article{sharma_4.4_2011,
      title = {A 4.4 {pJ/Access} 80 {MHz}, 128 kbit Variability Resilient {SRAM} With Multi-Sized Sense Amplifier Redundancy},
      volume = {46},
      issn = {0018-9200},
      doi = {10.1109/JSSC.2011.2159056},
      number = {10},
      journal = {{IEEE} Journal of Solid-State Circuits},
      author = {Sharma, V. and Cosemans, S. and Ashouei, M. and Huisken, J. and Catthoor, F. and Dehaene, W.},
      month = oct,
      year = {2011},
      keywords = {amplifiers, calibration, {CMOS} analogue integrated circuits, Energy consumption, energy-efficient hierarchical bit-line structure, frequency 80 {MHz}, global read sense amplifiers, {LP} {CMOS} process, {MS-SA-R} calibration technique, multisized {SA} redundancy calibration technique, multisized sense amplifier redundancy, size 90 nm, {SRAM} chips, variability resilient {SRAM}, {VDD-2} precharged short local bit-lines, wireless sensor applications, wireless sensor networks},
      pages = {2416 --2430},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\IFJ9NMUI\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\D94TDGZT\Sharma et al. - 2011 - A 4.4 pJAccess 80 MHz, 128 kbit Variability Resil.pdf:application/pdf}
    }
    
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  9. J. Hulzink et al., “An Ultra Low Energy Biomedical Signal Processing System Operating at Near-Threshold,” IEEE Transactions on Biomedical Circuits and Systems, vol. 5, no. 6, pp. 546–554, Dec. 2011. [Abstract] [BibTeX] [ CrossRef] This paper presents a voltage-scalable digital signal processing system designed for the use in a wireless sensor node (WSN) for ambulatory monitoring of biomedical signals. To fulfill the requirements of ambulatory monitoring, power consumption, which directly translates to the WSN battery lifetime and size, must be kept as low as possible. The proposed processing platform is an event-driven system with resources to run applications with different degrees of complexity in an energy-aware way. The architecture uses effective system partitioning to enable duty cycling, single instruction multiple data (SIMD) instructions, power gating, voltage scaling, multiple clock domains, multiple voltage domains, and extensive clock gating. It provides an alternative processing platform where the power and performance can be scaled to adapt to the application need. A case study on a continuous wavelet transform (CWT)-based heart-beat detection shows that the platform not only preserves the sensitivity and positive predictivity of the algorithm but also achieves the lowest energy/sample for ElectroCardioGram (ECG) heart-beat detection publicly reported today.
    @article{hulzink_ultra_2011,
      title = {An Ultra Low Energy Biomedical Signal Processing System Operating at Near-Threshold},
      volume = {5},
      issn = {1932-4545},
      url = {http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5746341},
      doi = {10.1109/TBCAS.2011.2176726},
      number = {6},
      journal = {{IEEE} Transactions on Biomedical Circuits and Systems},
      author = {Hulzink, J. and Konijnenburg, M. and Ashouei, M. and Breeschoten, A. and Berset, T. and Huisken, J. and Stuyt, J. and de Groot, H. and Barat, F. and David, J. and Van Ginderdeuren, J.},
      month = dec,
      year = {2011},
      keywords = {ambulatory monitoring, Ambulatory monitoring, battery lifetime, battery lifetime, continuous wavelet transform, continuous wavelet transform, duty cycling, duty cycling, {ECG}, {ECG}, electrocardiogram heart-beat detection, electrocardiogram heart-beat detection, electrocardiography, electrocardiography, event-driven system, event-driven system, extensive clock gating, extensive clock gating, heart-beat detection, heart-beat detection, medical signal detection, medical signal detection, medical signal processing, medical signal processing, multiple clock domains, multiple clock domains, multiple voltage domains, multiple voltage domains, near-threshold operation, near-threshold operation, patient monitoring, patient monitoring, power consumption, power consumption, power gating, power gating, single instruction multiple data instructions, single instruction multiple data instructions, ultralow energy biomedical signal processing system, ultralow energy biomedical signal processing system, voltage scaling, voltage scaling, voltage-scalable digital signal processing system, voltage-scalable digital signal processing system, wavelet transforms, wavelet transforms, wireless sensor networks, wireless sensor networks, wireless sensor node, wireless sensor node},
      pages = {546 --554}
    }
    
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  10. G. Selimis et al., “Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes,” in 2011 IEEE International Symposium on Circuits and Systems (ISCAS), 2011, pp. 567–570. [Abstract] [BibTeX] [ CrossRef] Due to the unattended nature of WSN (Wireless Sensor Network) deployment, each sensor can be subject to physical capture, cloning and unauthorized device alteration. In this paper, we use the embedded SRAM, often available on a wireless sensor node, for secure data (cryptographic keys, IDs) generation which is more resistant to physical attacks. We evaluate the physical phenomenon that the initial state of a 6T-SRAM cell is highly dependent on the process variations, which enables us to use the standard SRAM circuit, as a Physical Unclonable Function (PUF). Important requirements to serve as a PUF are that the start-up values of an SRAM circuit are uniquely determined, unpredictable and similar each time the circuit is turned on. We present the evaluation results of the internal SRAM memories of low power ICs as PUFs and the statistical analysis of the results. The experimental results prove that the low power 90nm commercial 6T-SRAMs are very useful as a PUF. As far as we know, this is the first work that provides an extensive evaluation of 6T-SRAM-based PUF, at different environmental, electrical, and ageing conditions to representing the typical operating conditions of a WSN.
    @inproceedings{selimis_evaluation_2011,
      title = {Evaluation of 90nm {6T-SRAM} as Physical Unclonable Function for secure key generation in wireless sensor nodes},
      doi = {10.1109/ISCAS.2011.5937628},
      booktitle = {2011 {IEEE} International Symposium on Circuits and Systems {(ISCAS)}},
      author = {Selimis, G. and Konijnenburg, M. and Ashouei, M. and Huisken, J. and de Groot, H. and van der Leest, V. and Schrijen, G.-J. and van Hulst, M. and Tuyls, P.},
      month = may,
      year = {2011},
      keywords = {{6T-SRAM}, cloning, cryptographic keys, cryptography, embedded {SRAM}, embedded systems, internal {SRAM} memory, physical capture, physical unclonable function, process variation, secure data, secure key generation, size 90 nm, {SRAM} chips, standard {SRAM} circuit, statistical analysis, telecommunication security, unauthorized device alteration, wireless sensor network, wireless sensor networks, wireless sensor node},
      pages = {567 --570},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\G239S9MK\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\S75T3249\Selimis et al. - 2011 - Evaluation of 90nm 6T-SRAM as Physical Unclonable .pdf:application/pdf}
    }
    
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  11. A. Artes, J. L. Ayala, A. V. Sathanur, J. Huisken, and F. Catthoor, “Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications,” in 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC), 2011, pp. 136–141. [Abstract] [BibTeX] [ CrossRef] Instruction memory organization is pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterized by restrictive resources and low energy budget, any enhancement in this component allows not only to decrease the total energy consumption, but also to have a better distribution of the energy budget throughout the system. This paper presents a self-tuning banked loop buffer architecture, which is based on a run-time loop buffer controller that optimizes both the dynamic and leakage energy consumption of the instruction memory organization. Results show that using banking in loop buffer architectures leads to higher reduction in the total energy consumption of the instruction memory organization if the tuning approach is applied sparingly. Based on post-layout simulations, our approach improves the total energy consumption by average of 20% in comparison with a loop buffer architecture based on a single monolithic memory, and more than 90% in comparison with instruction memory organizations without loop buffer architectures.
    @inproceedings{artes_run-time_2011,
      title = {Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications},
      doi = {10.1109/VLSISoC.2011.6081635},
      booktitle = {2011 {IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip {(VLSI-SoC)}},
      author = {Artes, A. and Ayala, {J.L.} and Sathanur, {A.V.} and Huisken, J. and Catthoor, F.},
      month = oct,
      year = {2011},
      keywords = {buffer circuits, buffer circuits, computer power supplies, computer power supplies, dynamic energy consumption, dynamic energy consumption, dynamic workload applications, dynamic workload applications, embedded systems, embedded systems, energy budget distribution, energy budget distribution, instruction memory organization, instruction memory organization, leakage energy consumption, leakage energy consumption, memory architecture, memory architecture, post-layout simulations, post-layout simulations, power optimization, power optimization, run-time loop buffer controller, run-time loop buffer controller, run-time self-tuning banked loop buffer architecture, run-time self-tuning banked loop buffer architecture, single monolithic memory, single monolithic memory, total energy consumption, total energy consumption},
      pages = {136 --141},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\E2NVKWC6\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\RRDJE8XN\Artes et al. - 2011 - Run-time self-tuning banked loop buffer architectu.pdf:application/pdf}
    }
    
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  12. Y. Zhang et al., “A 3.72 μW ultra-low power digital baseband for wake-up radios,” in 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2011, pp. 1–4. [Abstract] [BibTeX] [ CrossRef] In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72 #x03BC;W with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9 #x03BC;W.
    @inproceedings{zhang_3.72_2011,
      title = {A 3.72 {$\mu$}W ultra-low power digital baseband for wake-up radios},
      doi = {10.1109/VDAT.2011.5783586},
      booktitle = {2011 International Symposium on {VLSI} Design, Automation and Test {(VLSI-DAT)}},
      author = {Zhang, Yan and Chen, Sijie and Kiyani, {N.F.} and Dolmans, G. and Huisken, J. and Busze, B. and Harpe, P. and van der Meijs, N. and de Groot, H.},
      month = apr,
      year = {2011},
      keywords = {{CMOS} integrated circuits, {DBB} circuit, frequency 800 {kHz}, microwave circuits, packet detection performance, power 0.9 {muW}, power 3.72 {muW}, power channel monitoring, power consumption, radio receivers, size 90 nm, ultralow power digital baseband circuit, voltage 0.6 V, voltage 1.2 V, wake-up radio},
      pages = {1 --4},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\9MPBHAW8\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\F6T6DSMT\Zhang et al. - 2011 - A 3.72 #x03BC;W ultra-low power digital baseband f.pdf:application/pdf}
    }
    
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  13. H. Kim et al., “A configurable and low-power mixed signal SoC for portable ECG monitoring applications,” in 2011 Symposium on VLSI Circuits (VLSIC), 2011, pp. 142–143. [Abstract] [BibTeX] This paper describes a mixed-signal ECG System-on-chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel impedance measurement with high signal quality. A custom digital signal processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. The SoC is implemented in 0.18 #x03BC;m CMOS process and consumes minimum 31.1 #x03BC;W from a 1.2V.
    @inproceedings{kim_configurable_2011,
      title = {A configurable and low-power mixed signal {SoC} for portable {ECG} monitoring applications},
      booktitle = {2011 Symposium on {VLSI} Circuits {(VLSIC)}},
      author = {Kim, Hyejung and Yazicioglu, {R.F.} and Kim, Sunyoung and Van Helleputte, N. and Artes, A. and Konijnenburg, M. and Huisken, J. and Penders, J. and Van Hoof, C.},
      month = jun,
      year = {2011},
      keywords = {analog front-end, biomedical electronics, {CMOS} integrated circuits, {CMOS} process, configurable functionality, digital signal processing chips, digital signal processor, electric impedance, electrocardiography, low-power electronics, low-power mixed signal {SoC}, medical signal processing, mixed analogue-digital integrated circuits, motion artifact removal, patient monitoring, portable {ECG} monitoring applications, power 31.1 {muW}, R peak detection, single channel impedance measurement, size 0.18 mum, system-on-chip, voltage 1.2 V},
      pages = {142 --143},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\GFK5HJVB\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\92THNB65\Kim et al. - 2011 - A configurable and low-power mixed signal SoC for .pdf:application/pdf}
    }
    
    Details
  14. J. Zhou, M. Ashouei, D. Kinniment, J. Huisken, G. Russell, and A. Yakovlev, “Sub-threshold synchronizer,” Microelectronics Journal, 2011. [BibTeX]
    @article{zhou_sub-threshold_2011,
      title = {Sub-threshold synchronizer},
      journal = {Microelectronics Journal},
      author = {Zhou, J. and Ashouei, M. and Kinniment, D. and Huisken, J. and Russell, G. and Yakovlev, A.},
      year = {2011}
    }
    
    Details
  15. F. Bouwens et al., “A dual-core system solution for wearable health monitors,” in Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, New York, NY, USA, 2011, pp. 379–382. [Abstract] [BibTeX] [ CrossRef] This paper presents a system design study for wearable sensor devices intended for healthcare and lifestyle applications based on ECG, EEG and activity monitoring. In order to meet the low-power requirement of these applications, a dual-core signal processing system is proposed which combines an ultra-low-power bio-medical Application Specific Instruction-set Processor (BioASIP) and a low-power general-purpose micro-controller (MSP430). To validate the merits of the proposed architecture, system-level power analysis and trade-offs are conducted using real hardware measurements of an ECG R-peak detection application. The results show that the proposed dual-core architecture consumes around 65.38µW, about 25.8x smaller than an MSP430-only approach. Out of 65.38µW, the BioASIP consumes only 11µW and the rest is used in the analog front-end, A/D conversion, and control tasks.
    @inproceedings{bouwens_dual-core_2011,
      address = {New York, {NY}, {USA}},
      series = {{GLSVLSI} '11},
      title = {A dual-core system solution for wearable health monitors},
      isbn = {978-1-4503-0667-6},
      url = {http://doi.acm.org/10.1145/1973009.1973087},
      doi = {10.1145/1973009.1973087},
      urldate = {2012-03-19},
      booktitle = {Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on {VLSI}},
      publisher = {{ACM}},
      author = {Bouwens, Frank and Huisken, Jos and De Groot, Harmke and Bennebroek, Martijn and Abbo, Anteneh and Santana, Octavio and van Meerbergen, Jef and Fraboulet, Antoine},
      year = {2011},
      keywords = {application specific instruction-set processor, {BioASIP}, biomedical processing, low power, system level simulation, {WSim}},
      pages = {379–382}
    }
    
    Details
  16. M. Vidojkovic et al., “A 2.4 GHz ULP OOK Single-Chip Transceiver for Healthcare Applications,” IEEE Transactions on Biomedical Circuits and Systems, vol. 5, no. 6, pp. 523–534, Dec. 2011. [Abstract] [BibTeX] [ CrossRef] This paper describes an ultra-low power (ULP) single chip transceiver for wireless body area network (WBAN) applications. It supports on-off keying (OOK) modulation, and it operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands. It is implemented in 90 nm CMOS technology. The direct modulated transmitter transmits OOK signal with 0 dBm peak power, and it consumes 2.59 mW with 50% OOK. The transmitter front-end supports up to 10 Mbps. The transmitter digital baseband enables digital pulse-shaping to improve spectrum efficiency. The super-regenerative receiver front-end supports up to 5 Mbps with -75 dBm sensitivity. Including the digital part, the receiver consumes 715 #x03BC;W at 1 Mbps data rate, oversampled at 3 MHz. At the system level the transceiver achieves PER=10 ^\textrm-2 at 25 meters line of site with 62.5 kbps data rate and 288 bits packet size. The transceiver is integrated in an electrocardiogram (ECG) necklace to monitor the heart’s electrical property.
    @article{vidojkovic_2.4_2011,
      title = {A 2.4 {GHz} {ULP} {OOK} Single-Chip Transceiver for Healthcare Applications},
      volume = {5},
      issn = {1932-4545},
      doi = {10.1109/TBCAS.2011.2173340},
      number = {6},
      journal = {{IEEE} Transactions on Biomedical Circuits and Systems},
      author = {Vidojkovic, M. and Huang, X. and Harpe, P. and Rampu, S. and Zhou, C. and Huang, L. and van de Molengraft, J. and Imamura, K. and Busze, B. and Bouwens, F. and Konijnenburg, M. and Santana, J. and Breeschoten, A. and Huisken, J. and Philips, K. and Dolmans, G. and de Groot, H.},
      month = dec,
      year = {2011},
      keywords = {amplitude shift keying, bioelectric potentials, biomedical electronics, Body area networks, {CMOS} technology, digital pulse shaping, direct modulated transmitter, {ECG} necklace, electrocardiogram, electrocardiography, frequency 2.4 {GHz}, health care, healthcare application, on-off keying modulation, patient monitoring, pulse shaping, size 90 nm, super regenerative receiver front end, transceivers, transmitter digital baseband, {ULP} {OOK} single chip transceiver, ultra low power single chip transceiver, {WBAN} application, wireless body area network, wireless sensor networks},
      pages = {523 --534},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\32WHCSTX\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\DJSK266X\Vidojkovic et al. - 2011 - A 2.4 GHz ULP OOK Single-Chip Transceiver for Heal.pdf:application/pdf}
    }
    
    Details
  17. M. Vidojkovic et al., “A 2.4GHz ULP OOK single-chip transceiver for healthcare applications,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International, 2011, pp. 458–460. [Abstract] [BibTeX] [ CrossRef] Wireless body-area networks (WBAN) are used for communication among sensor nodes operating on, in or around the human body, e.g. for healthcare purposes. In view of energy autonomy, the total energy consumption of the sensor nodes should be minimized. Because of their low complexity, a combination of the super-regenerative (SR) principle [1-3] and OOK modulation enables ultra low power (ULP) consumption. This work presents a 2.4GHz ULP OOK single chip transceiver for WBAN applications. A block diagram of the implemented transceiver is shown in Fig. 26.3.1. Next to the direct modulation TX [4] and SR RF [5] front-ends, this work integrates analog and digital baseband, PLL functionality and additional programmability for flexible data rates, and achieves ultra-low power consumption for the overall system.
    @inproceedings{vidojkovic_2.4ghz_2011,
      title = {A {2.4GHz} {ULP} {OOK} single-chip transceiver for healthcare applications},
      doi = {10.1109/ISSCC.2011.5746396},
      booktitle = {Solid-State Circuits Conference Digest of Technical Papers {(ISSCC)}, 2011 {IEEE} International},
      author = {Vidojkovic, M. and Huang, Xiongchuan and Harpe, P. and Rampu, S. and Zhou, Cui and Huang, Li and Imamura, K. and Busze, B. and Bouwens, F. and Konijnenburg, M. and Santana, J. and Breeschoten, A. and Huisken, J. and Dolmans, G. and de Groot, H.},
      month = feb,
      year = {2011},
      keywords = {analog baseband, analog baseband, block diagram, block diagram, body area networks, Body area networks, body sensor networks, Body sensor networks, digital baseband, digital baseband, direct modulation {TX}, direct modulation {TX}, frequency 2.4 {GHz}, frequency 2.4 {GHz}, health care, health care, healthcare applications, healthcare applications, low-power electronics, low-power electronics, {OOK} modulation, {OOK} modulation, phase locked loops, phase locked loops, {PLL}, {PLL}, sensor node energy autonomy, sensor node energy autonomy, sensor node energy consumption, sensor node energy consumption, {SR} {RF} front-ends, {SR} {RF} front-ends, super-regenerative principle, super-regenerative principle, transceivers, transceivers, {ULP} {OOK} single chip transceiver, {ULP} {OOK} single chip transceiver, {ULP} {OOK} single-chip transceiver, {ULP} {OOK} single-chip transceiver, ultra low power consumption, ultra low power consumption, ultra-low power consumption, ultra-low power consumption, {WBAN}, {WBAN}, wireless body-area networks, wireless body-area networks},
      pages = {458 --460},
      annote = {Wireless body-area networks {(WBAN)} are used for communication among sensor nodes operating on, in or around the human body, e.g. for healthcare purposes. In view of energy autonomy, the total energy consumption of the sensor nodes should be minimized. Because of their low complexity, a combination of the super-regenerative {(SR)} principle [1-3] and {OOK} modulation enables ultra low power {(ULP)} consumption. This work presents a {2.4GHz} {ULP} {OOK} single chip transceiver for {WBAN} applications. A block diagram of the implemented transceiver is shown in Fig. 26.3.1. Next to the direct modulation {TX} [4] and {SR} {RF} [5] front-ends, this work integrates analog and digital baseband, {PLL} functionality and additional programmability for flexible data rates, and achieves ultra-low power consumption for the overall system.},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\TA559C58\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\NPHUWVCU\Vidojkovic et al. - 2011 - A 2.4GHz ULP OOK single-chip transceiver for healt.pdf:application/pdf}
    }
    
    Details
  18. M. Ashouei et al., “A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4V,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International, 2011, pp. 332–334. [BibTeX]
    @inproceedings{ashouei_voltage-scalable_2011,
      title = {A voltage-scalable biomedical signal processor running {ECG} using {13pJ/cycle} at {1MHz} and {0.4V}},
      isbn = {0193-6530},
      booktitle = {Solid-State Circuits Conference Digest of Technical Papers {(ISSCC)}, 2011 {IEEE} International},
      author = {Ashouei, M. and Hulzink, J. and Konijnenburg, M. and Zhou, Jun and Duarte, F. and Breeschoten, A. and Huisken, J. and Stuyt, J. and de Groot, H. and Barat, F. and David, J. and Van Ginderdeuren, J.},
      year = {2011},
      keywords = {biomedical equipment, biomedical equipment, clock gating, clock gating, digital signal processing chips, digital signal processing chips, duty cycling, duty cycling, {ECG} algorithm, {ECG} algorithm, electrocardiography, electrocardiography, electroencephalography, Electroencephalography, event driven system, event driven system, feature extraction, feature extraction, medical signal processing, medical signal processing, motion artifact cancellation, motion artifact cancellation, multichannel {EEG} processing, multichannel {EEG} processing, parallel processing, parallel processing, power gating, power gating, {SIMD} instruction, {SIMD} instruction, system partitioning, system partitioning, voltage 0.4 V to 1.2 V, voltage 0.4 V to 1.2 V, voltage scalable biomedical signal processor, voltage scalable biomedical signal processor},
      pages = {332--334},
      annote = {In this paper, the authors present an event-driven system with resources to run applications with different degrees of complexity in an energy-aware way. The architecture uses effective system partitioning to enable duty cycling, {SIMD} instructions, power gating, voltage scaling, multiclock domains, multivoltage domains, and extensive clock gating. The system has sufficient computational power to run a complex {ECG} algorithm with feature extraction and motion artifact cancellation or multichannel {EEG} processing. The system consumes an average of 13 {pJ/cycle} running a {CWT-based} {ECG} application at 0.4 V. The processor can run at voltage range of 0.4 to 1.2 V and supports frequency range of 1 to 100 {MHz.} The system has comparable energy/cycle, more computation capability, and larger available frequencies than the previously reported complex designs in the works of Sindhara et al. [2010] and Chen et al. [2010].},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\DGX6PUTG\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\IQP4CQ6E\Ashouei et al. - 2011 - A voltage-scalable biomedical signal processor run.pdf:application/pdf}
    }
    
    Details
  19. V. Sharma, S. Cosemans, M. Ashouei, J. Huisken, F. Catthoor, and W. Dehaene, “8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes,” in ESSCIRC (ESSCIRC), 2011 Proceedings of the, 2011, pp. 531–534. [Abstract] [BibTeX] [ CrossRef] This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 11.36fJ/decision and obtains #x03C3;Voffset of 14.297mV without requiring calibration.
    @inproceedings{sharma_8t_2011,
      title = {{8T} {SRAM} with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes},
      doi = {10.1109/ESSCIRC.2011.6044939},
      booktitle = {{ESSCIRC} {(ESSCIRC)}, 2011 Proceedings of the},
      author = {Sharma, V. and Cosemans, S. and Ashouei, M. and Huisken, J. and Catthoor, F. and Dehaene, W.},
      month = sep,
      year = {2011},
      keywords = {{8T} {SRAM}, {8T} {SRAM}, charge limited sequential sense amplifier, charge limited sequential sense amplifier, {CMOS} memory circuits, {CMOS} memory circuits, embedded {SRAM}, embedded {SRAM}, low energy consumption, low energy consumption, low-power electronics, low-power electronics, {LP} {CMOS}, {LP} {CMOS}, mimicked negative bit-lines, mimicked negative bit-lines, random-access storage, random-access storage, {SRAM} macro, {SRAM} macro, wireless sensor networks, wireless sensor networks, wireless sensor nodes, wireless sensor nodes},
      pages = {531 --534},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\PI5ST977\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\86W69FZC\Sharma et al. - 2011 - 8T SRAM with Mimicked Negative Bit-lines and Charg.pdf:application/pdf}
    }
    
    Details
  20. J. Zhou, S. Jayapal, J. Stuyt, J. Huisken, and H. de Groot, “The impact of inverse narrow width effect on sub-threshold device sizing,” in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, pp. 267–272. [Abstract] [BibTeX] [ CrossRef] Sub-threshold operation has been proved to be successful to achieve minimum energy consumption. It is well known that the sub-threshold device sizing is different from super-threshold due to different current behavior. The previously reported sub-threshold sizing methods assume that the current is proportional to the transistor width. However, we have found that the inverse narrow width effect has a significant influence on the threshold voltage in the sub-threshold region, causing non-proportional current-width relationship. Sizing without considering this effect may result in significant imbalance in the rise and fall delay which degrades the performance, power consumption and the functional yield of the design. We have proposed a new sub-threshold sizing method to balance the rise and fall delay by taking into account the influence of inverse narrow width effect while minimizing the transistor size. Compared with the previous sub-threshold sizing method the delay and power-delay-product (PDP) are reduced by up to 35.4% and 73.4% with up to 57% saving in the area. Further, due to symmetric rise and fall delay the minimum operating voltage can be lowered by 8% which leads to another 16% of energy reduction.
    @inproceedings{zhou_impact_2011,
      title = {The impact of inverse narrow width effect on sub-threshold device sizing},
      doi = {10.1109/ASPDAC.2011.5722196},
      booktitle = {Design Automation Conference {(ASP-DAC)}, 2011 16th Asia and South Pacific},
      author = {Zhou, Jun and Jayapal, S. and Stuyt, J. and Huisken, J. and de Groot, H.},
      month = jan,
      year = {2011},
      keywords = {inverse narrow width effect, inverse narrow width effect, low-power electronics, low-power electronics, {MOSFET}, {MOSFET}, nonproportional current-width relationship, nonproportional current-width relationship, power consumption, power consumption, power delay product, power delay product, subthreshold device sizing, subthreshold device sizing, transistor width, transistor width},
      pages = {267 --272},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\SN3UKGMA\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\DZZ5U8GC\Zhou et al. - 2011 - The impact of inverse narrow width effect on sub-t.pdf:application/pdf}
    }
    
    Details
  21. Y. Zhang et al., “A 3.72\muW ultra-low power digital baseband for wake-up radios,” in VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on, 2011, pp. 1–4. [Abstract] [BibTeX] In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72μW with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9μW.
    @inproceedings{yan_zhang_3.72w_2011,
      title = {A {3.72$\mu$W} ultra-low power digital baseband for wake-up radios},
      isbn = {Pending},
      booktitle = {{VLSI} Design, Automation and Test {(VLSI-DAT)}, 2011 International Symposium on},
      author = {Zhang, Yan and Chen, Sijie and Kiyani, {N.F.} and Dolmans, G. and Huisken, J. and Busze, B. and Harpe, P. and van der Meijs, N. and de Groot, H.},
      year = {2011},
      keywords = {{CMOS} integrated circuits, {DBB} circuit, frequency 800 {kHz}, microwave circuits, packet detection performance, power 0.9 {muW}, power 3.72 {muW}, power channel monitoring, power consumption, radio receivers, size 90 nm, ultralow power digital baseband circuit, voltage 0.6 V, voltage 1.2 V, wake-up radio},
      pages = {1--4}
    }
    
    Details
  22. A. Niedermeier, K. Svarstad, F. Bouwens, J. Hulzink, and J. Huisken, “The challenges of implementing fine-grained power gating,” in Proceedings of the 20th symposium on Great lakes symposium on VLSI, New York, NY, USA, 2010, pp. 361–364. [BibTeX] [ CrossRef]
    @inproceedings{Niedermeier:2010:CIF:1785481.1785564,
      author = {Niedermeier, Anja and Svarstad, Kjetil and Bouwens, Frank and Hulzink, Jos and Huisken, Jos},
      title = {The challenges of implementing fine-grained power
                        gating},
      booktitle = {Proceedings of the 20th symposium on Great lakes
                        symposium on VLSI},
      series = {GLSVLSI '10},
      year = {2010},
      isbn = {978-1-4503-0012-4},
      location = {Providence, Rhode Island, USA},
      pages = {361--364},
      numpages = {4},
      url = {http://doi.acm.org/10.1145/1785481.1785564},
      doi = {http://doi.acm.org/10.1145/1785481.1785564},
      acmid = {1785564},
      publisher = {ACM},
      address = {New York, NY, USA},
      keywords = {analysis, leakage power minimization, power gating,
                        power management, power modeling,
                        register-transfer-level}
    }
    
    Details
  23. S. Jayapal, J. Stuijt, J. Huisken, and Y. Manoli, “Energy efficient computation with self-adaptive single-ended body bias,” in SOC Conference (SOCC), 2010 IEEE International, 2010, pp. 326–329. [Abstract] [BibTeX] Energy efficient computation becomes increasingly important for battery driven ubiquitous computing applications. To extend the battery life time while still meeting the performance demands, the designers face critical challenges in choosing the appropriate circuit topologies and low-power design techniques in order to optimally balance the power and performance trade-offs. In this paper, we evaluate various form of single-ended body bias configuration and experimented the fine-grained self-adaptive circuit optimization technique such as pull-up body bias and pull-down body bias to combine the monotonic precharge-evaluate logic circuits and application of body bias based on the evaluation and idle modes within logic stages. This technique improves the evaluation delay by 19% and 16% with 15% and 10% lower energy consumption for the non-clocked and clocked 16-bit CLA adder respectively.
    @inproceedings{jayapal_energy_2010,
      title = {Energy efficient computation with self-adaptive single-ended body bias},
      isbn = {Pending},
      booktitle = {{SOC} Conference {(SOCC)}, 2010 {IEEE} International},
      author = {Jayapal, S. and Stuijt, J. and Huisken, J. and Manoli, Y.},
      year = {2010},
      keywords = {battery driven ubiquitous computing, battery driven ubiquitous computing, battery life time, battery life time, circuit topologies, circuit topologies, energy conservation, energy conservation, energy efficient computation, energy efficient computation, fine-grained self-adaptive circuit optimization technique, fine-grained self-adaptive circuit optimization technique, logic design, logic design, low-power design techniques, low-power design techniques, monotonic precharge-evaluate logic circuits, monotonic precharge-evaluate logic circuits, network topology, network topology, optimisation, optimisation, self-adaptive single-ended body bias, self-adaptive single-ended body bias, self-adjusting systems, self-adjusting systems, ubiquitous computing, ubiquitous computing},
      pages = {326--329},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\AAQ2TKWK\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\RZ4T6K9C\Jayapal et al. - 2010 - Energy efficient computation with self-adaptive si.pdf:application/pdf}
    }
    
    Details
  24. M. Ashouei, H. Luijmes, J. Stuijt, and J. Huisken, “Novel wide voltage range level shifter for near-threshold designs,” in 2010 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010, pp. 285–288. [Abstract] [BibTeX] [ CrossRef] This paper presents a novel low-to-high level shifter that enables having voltage domains with substantially different supply voltages from near-threshold to full supply voltage. The level shifter was designed in a 90 nm CMOS technology and uses thick-oxide transistors, non-minimum channel length transistors, along with novel circuit structures to up convert from 0.36 V to 1.32 V and all the voltage levels in between for all process corners and the temperature range of [0 #x00B0;C - 125 #x00B0;C]. Relaxing the temperature operating range to [25 #x00B0;C - 125 #x00B0;C], the level shifter works deep into the sub threshold region capable of up converting from 0.31 V to 1.32 V. For the typical case operating condition, the proposed level shifter has an unprecedented performance of 1.5 ns while up converting 0.36 V to 1.32 V.
    @inproceedings{ashouei_novel_2010,
      title = {Novel wide voltage range level shifter for near-threshold designs},
      doi = {10.1109/ICECS.2010.5724509},
      booktitle = {2010 17th {IEEE} International Conference on Electronics, Circuits, and Systems {(ICECS)}},
      author = {Ashouei, M. and Luijmes, H. and Stuijt, J. and Huisken, J.},
      month = dec,
      year = {2010},
      keywords = {{CMOS} analogue integrated circuits, {CMOS} analogue integrated circuits, {CMOS} technology, {CMOS} technology, convertors, convertors, low-power electronics, low-power electronics, near-threshold design, near-threshold design, non-minimum channel length transistor, non-minimum channel length transistor, size 90 nm, size 90 nm, temperature 0 {degC} to 125 {degC}, temperature 0 {degC} to 125 {degC}, thick-oxide transistor, thick-oxide transistor, time 1.5 ns, time 1.5 ns, transistors, transistors, voltage 0.31 V to 1.32 V, voltage 0.31 V to 1.32 V, voltage range low-to-high level shifter, voltage range low-to-high level shifter},
      pages = {285 --288},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\ITVT3DBH\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\Z4ZH4JWQ\Ashouei et al. - 2010 - Novel wide voltage range level shifter for near-th.pdf:application/pdf}
    }
    
    Details
  25. B. Busze et al., “Ultra Low Power programmable biomedical SoC for on-body ECG and EEG processing,” in Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian, 2010, pp. 1–4. [Abstract] [BibTeX] [ CrossRef] An Ultra Low Power (ULP) biomedical System-on Chip (SoC) has been developed for efficient ECG/EEG signal processing in a Body Area Network environment. This experimental SoC explores the use of event-driven peripheral modules that autonomously interact with external sensors together with the use of an Application-Specific-Instruction-set Processor (ASIP) to optimize energy-efficiency during active and sleep periods. The SoC has been manufactured in standard 90nm CMOS process and use has been made of power gating to reduce leakage power that starts to become more dominant in advanced technologies. When running an ECG algorithm that is capable of reliably detecting the QRS complex in an ambulatory environment, an average power consumption of 10 #x03BC;W has been measured at 0.7 V supply.
    @inproceedings{busze_ultra_2010,
      title = {Ultra Low Power programmable biomedical {SoC} for on-body {ECG} and {EEG} processing},
      doi = {10.1109/ASSCC.2010.5716625},
      booktitle = {Solid State Circuits Conference {(A-SSCC)}, 2010 {IEEE} Asian},
      author = {Busze, B. and Bouwens, F. and Konijnenburg, M. and De Nil, M. and Ashouei, M. and Hulzink, J. and Zhou, J. and Stuyt, J. and Huisken, J. and de Groot, H. and Santana, O. and Abbo, A. and Yseboodt, L. and van Meerbergen, J. and Bennebroek, M.},
      month = nov,
      year = {2010},
      keywords = {ambulatory environment, ambulatory environment, application-specific-instruction-set-processor, application-specific-instruction-set-processor, biomedical electronics, Biomedical electronics, body area network environment, body area network environment, body area networks, Body area networks, {CMOS} integrated circuits, {CMOS} integrated circuits, {CMOS} processing, {CMOS} processing, {ECG} signal processing, {ECG} signal processing, {EEG} signal processing, {EEG} signal processing, electrocardiography, electrocardiography, electroencephalography, Electroencephalography, event-driven peripheral modules, event-driven peripheral modules, leakage power, leakage power, medical signal processing, medical signal processing, power 10 {muW}, power 10 {muW}, power consumption, power consumption, power gating, power gating, size 90 nm, size 90 nm, sleep, Sleep, system-on-chip, system-on-chip, ultralow power biomedical system-on-chip, ultralow power biomedical system-on-chip},
      pages = {1 --4},
      annote = {An Ultra Low Power {(ULP)} biomédical System-on-Chip {(SoC)} has been developed for efficient {ECG/EEG} signal processing in a Body Area Network environment. This experimental {SoC} explores the use of event-driven peripheral modules that autonomously interact with external sensors together with the use of an Application-Specific-Instruction-set-Processor {(ASIP)} to optimize energy-efficiency during active and sleep periods. The {SoC} has been manufactured in standard 90nm {CMOS} process and use has been made of power gating to reduce leakage power that starts to become more dominant in advanced technologies. When running an {ECG} algorithm that is capable of reliably detecting the {QRS} complex in an ambulatory environment, an average power consumption of 10 {μW} has been measured at 0.7 V supply.},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\23ZV9NEU\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\HZHAWM3X\Bu&#x0308 andsze et al. - 2010 - Ultra Low Power programmable biomedical SoC for on.pdf:application/pdf}
    }
    
    Details
  26. I. Tsekoura et al., “Exploration of cryptographic ASIP designs for wireless sensor nodes,” in 2010 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010, pp. 827–830. [Abstract] [BibTeX] [ CrossRef] We present the design of 4 Application Specific Instruction Set Processors (8-bit, 32-bit, 64-bit and 128-bit ASIP) which provide typical 16-bit general instructions and accelerate a common cryptographic domain. The ASIPs support the following security services: data confidentiality, data authentication, data integrity and replay attack protection and their design is appropriate for wireless sensor networks. The corresponding software for each ASIP has been optimized in terms of clock cycles and memory accesses. We evaluate the 4 ASIPs in terms of performance, power consumption, energy dissipation and area occupation. When our most energy efficient design (128-bit ASIP) operates on AES-CCM-32 security mode at a clock frequency of 100 MHz, it dissipates 41.86 nJ achieving a maximum throughput of 21.76 Mbps, while at a lower clock frequency of 4.61 MHz, it achieves a throughput of 1 Mbps, a typical value in the WSN, and dissipates energy of 35.20 nJ. The corresponding area overhead, for 90nm technology, excluding the memories, is 34.3K NAND2 equivalents. Comparisons with other works are given.
    @inproceedings{tsekoura_exploration_2010,
      title = {Exploration of cryptographic {ASIP} designs for wireless sensor nodes},
      doi = {10.1109/ICECS.2010.5724640},
      booktitle = {2010 17th {IEEE} International Conference on Electronics, Circuits, and Systems {(ICECS)}},
      author = {Tsekoura, I. and Selimis, G. and Hulzink, J. and Catthoor, F. and Huisken, J. and de Groot, H. and Goutis, C.},
      month = dec,
      year = {2010},
      keywords = {{AES-CCM-32} security mode, {AES-CCM-32} security mode, application specific instruction set processors, Application Specific Instruction Set Processors, application specific integrated circuits, application specific integrated circuits, clock frequency, clock frequency, clocks, Clocks, cryptographic {ASIP} designs, cryptographic {ASIP} designs, cryptography, cryptography, data authentication, data authentication, data confidentiality, data confidentiality, digital signal processing chips, digital signal processing chips, energy dissipation, Energy dissipation, frequency 100 {MHz}, frequency 100 {MHz}, frequency 4.61 {MHz}, frequency 4.61 {MHz}, instruction set processors, instruction set processors, power consumption, power consumption, programmable {DSP}, programmable {DSP}, size 90 nm, size 90 nm, wireless sensor networks, wireless sensor networks, wireless sensor nodes, wireless sensor nodes},
      pages = {827 --830},
      file = {IEEE Xplore Abstract Record:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\W9FJ2Q9I\articleDetails.html:text/html;IEEE Xplore Full Text PDF:C:\Users\Jos\AppData\Roaming\Mozilla\Firefox\Profiles\x8q5fzo7.default\zotero\storage\4Z4JUCXA\Tsekoura et al. - 2010 - Exploration of cryptographic ASIP designs for wire.pdf:application/pdf}
    }
    
    Details
  27. A. Hansson, K. Goossens, M. Bekooij, and J. Huisken, “CoMPSoC: A template for composable and predictable multi-processor system on chips,” ACM Trans. Des. Autom. Electron. Syst., vol. 14, no. 1, pp. 2:1–2:24, Jan. 2009. [BibTeX] [ CrossRef]
    @article{Hansson:2009:CTC:1455229.1455231,
      author = {Hansson, Andreas and Goossens, Kees and Bekooij, Marco and Huisken, Jos},
      title = {{CoMPSoC}: A template for composable and predictable
                        multi-processor system on chips},
      journal = {ACM Trans. Des. Autom. Electron. Syst.},
      volume = {14},
      issue = {1},
      month = jan,
      year = {2009},
      issn = {1084-4309},
      pages = {2:1--2:24},
      articleno = {2},
      numpages = {24},
      url = {http://doi.acm.org/10.1145/1455229.1455231},
      doi = {http://doi.acm.org/10.1145/1455229.1455231},
      acmid = {1455231},
      publisher = {ACM},
      address = {New York, NY, USA},
      keywords = {Composable, model of computation, network on chip,
                        predictable, system on chip}
    }
    
    Details
  28. L. Yseboodt et al., “Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring,” J. Signal Process. Syst., vol. 57, no. 1, pp. 107–119, Oct. 2009. [BibTeX] [ CrossRef]
    @article{Yseboodt:2009:DWS:1569405.1569413,
      author = {Yseboodt, Lennart and Nil, Michael and Huisken, Jos and Berekovic, Mladen and Zhao, Qin and Bouwens, Frank and Hulzink, Jos and Meerbergen, Jef},
      title = {Design of 100 $\mu${W} Wireless Sensor Nodes for
                        Biomedical Monitoring},
      journal = {J. Signal Process. Syst.},
      volume = {57},
      issue = {1},
      month = oct,
      year = {2009},
      issn = {1939-8018},
      pages = {107--119},
      numpages = {13},
      url = {http://portal.acm.org/citation.cfm?id=1569405.1569413},
      doi = {10.1007/s11265-008-0255-x},
      acmid = {1569413},
      publisher = {Kluwer Academic Publishers},
      address = {Hingham, MA, USA},
      keywords = {ASIP, Clock gating, ECG, Low power, Wireless sensor
                        node}
    }
    
    Details
  29. J. Govers et al., “Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP,” in Proceedings of the 3rd international conference on High performance embedded architectures and compilers, Berlin, Heidelberg, 2008, pp. 82–96. [BibTeX]
    @inproceedings{Govers:2008:IUI:1786054.1786064,
      author = {Govers, Jochem and Huisken, Jos and Berekovic, Mladen and Rousseaux, Olivier and Bouwens, Frank and de Nil, Michael and Van Meerbergen, Jef},
      title = {Implementation of an {UWB} impulse-radio acquisition
                        and despreading algorithm on a low power {ASIP}},
      booktitle = {Proceedings of the 3rd international conference on
                        High performance embedded architectures and
                        compilers},
      series = {HiPEAC'08},
      year = {2008},
      isbn = {3-540-77559-5, 978-3-540-77559-1},
      location = {G\&\#246;teborg, Sweden},
      pages = {82--96},
      numpages = {15},
      url = {http://portal.acm.org/citation.cfm?id=1786054.1786064},
      acmid = {1786064},
      publisher = {Springer-Verlag},
      address = {Berlin, Heidelberg}
    }
    
    Details
  30. J. Huisken, “Integrating VLIW processors with a network on chip,” in Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation, Berlin, Heidelberg, 2007, pp. 2–2. [BibTeX]
    @inproceedings{Huisken:2007:IVP:1776200.1776203,
      author = {Huisken, Jos},
      title = {Integrating {VLIW} processors with a network on chip},
      booktitle = {Proceedings of the 7th international conference on
                        Embedded computer systems: architectures, modeling,
                        and simulation},
      series = {SAMOS'07},
      year = {2007},
      isbn = {3-540-73622-0, 978-3-540-73622-6},
      location = {Samos, Greece},
      pages = {2--2},
      numpages = {1},
      url = {http://portal.acm.org/citation.cfm?id=1776200.1776203},
      acmid = {1776203},
      publisher = {Springer-Verlag},
      address = {Berlin, Heidelberg}
    }
    
    Details
  31. L. Yseboodt et al., “Design of 100 μW wireless sensor nodes on energy scavengers for biomedical monitoring,” in Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation, Berlin, Heidelberg, 2007, pp. 385–395. [BibTeX]
    @inproceedings{Yseboodt:2007:DWS:1776200.1776251,
      author = {Yseboodt, Lennart and De Nil, Michael and Huisken, Jos and Berekovic, Mladen and Zhao, Qin and Bouwens, Frank and Van Meerbergen, Jef},
      title = {Design of 100 $\mu${W} wireless sensor nodes on
                        energy scavengers for biomedical monitoring},
      booktitle = {Proceedings of the 7th international conference on
                        Embedded computer systems: architectures, modeling,
                        and simulation},
      series = {SAMOS'07},
      year = {2007},
      isbn = {3-540-73622-0, 978-3-540-73622-6},
      location = {Samos, Greece},
      pages = {385--395},
      numpages = {11},
      url = {http://portal.acm.org/citation.cfm?id=1776200.1776251},
      acmid = {1776251},
      publisher = {Springer-Verlag},
      address = {Berlin, Heidelberg}
    }
    
    Details
  32. J. Leijten, G. Burns, J. Huisken, E. Waterlander, and A. van Wel, “AVISPA: a massively parallel reconfigurable accelerator,” in Proceedings. International Symposium on System-on-Chip., 2003, pp. 165–168. [BibTeX]
    @inproceedings{leijten03,
      author = {Leijten, J. and Burns, G. and Huisken, J. and Waterlander, E. and van Wel, A.},
      title = {{AVISPA}: a massively parallel reconfigurable
                        accelerator},
      booktitle = {Proceedings. International Symposium on
                        System-on-Chip.},
      pages = {165 - 168},
      year = {2003},
      month = nov
    }
    
    Details
  33. L. T. Smit, G. J. M. Smit, P. J. M. Havinga, J. A. Huisken, K. G. W. Goossens, and J. T. M. H. Dielissen, “Towards A Model for Making A Trade-off Between QoS And Costs,” in Proceedings of the CTIT workshop. Mobile Communications in perspective, 2001. [BibTeX]
    @inproceedings{Smit01a,
      author = {Smit, Lodewijk T. and Smit, Gerard J.M. and Havinga, Paul J.M. and Huisken, Jos A. and Goossens, Kees G.W. and Dielissen, John T.M.H.},
      title = {Towards A Model for Making A Trade-off Between {QoS}
                        And Costs},
      booktitle = {Proceedings of the {CTIT} workshop. Mobile
                        Communications in perspective},
      year = {2001},
      month = feb
    }
    
    Details
  34. J. Dielissen et al., “Power-efficient layered turbo decoder processor,” in Proceedings of the conference on Design, automation and test in Europe, Piscataway, NJ, USA, 2001, pp. 246–251. [BibTeX]
    @inproceedings{Dielissen:2001:PLT:367072.367201,
      author = {Dielissen, J. and van Meerbergen, J. and Bekooij, M. and Harmsze, F. and Sawitzki, S. and Huisken, J. and van der Werf, A.},
      title = {Power-efficient layered turbo decoder processor},
      booktitle = {Proceedings of the conference on Design, automation
                        and test in Europe},
      series = {DATE '01},
      year = {2001},
      isbn = {0-7695-0993-2},
      location = {Munich, Germany},
      pages = {246--251},
      numpages = {6},
      url = {http://portal.acm.org/citation.cfm?id=367072.367201},
      acmid = {367201},
      publisher = {IEEE Press},
      address = {Piscataway, NJ, USA}
    }
    
    Details
  35. M. Bekooij, J. Huisken, and K. Nowak, “Numerical Accuracy of Fast Fourier Transforms with CORDIC Arithmetic,” J. VLSI Signal Process. Syst., vol. 25, no. 2, pp. 187–193, Jun. 2000. [BibTeX] [ CrossRef]
    @article{Bekooij:2000:NAF:352135.352189,
      author = {Bekooij, M. and Huisken, J. and Nowak, K.},
      title = {Numerical Accuracy of Fast Fourier Transforms with
                        {CORDIC} Arithmetic},
      journal = {J. VLSI Signal Process. Syst.},
      volume = {25},
      issue = {2},
      month = jun,
      year = {2000},
      issn = {0922-5773},
      pages = {187--193},
      numpages = {7},
      url = {http://portal.acm.org/citation.cfm?id=352135.352189},
      doi = {10.1023/A:1008179225059},
      acmid = {352189},
      publisher = {Kluwer Academic Publishers},
      address = {Hingham, MA, USA}
    }
    
    Details
  36. F. van de Laar, N. Philips, and J. Huisken, “Towards the next generation of DAB receivers,” EBU Technical Review, no. 272, pp. 46–59, 1997. [BibTeX]
    @article{laar97,
      author = {van de Laar, Frank and Philips, Norbert and Huisken, Jos},
      title = {{Towards the next generation of DAB receivers}},
      journal = {{EBU Technical Review}},
      year = {1997},
      number = {272},
      pages = {46-59},
      month = {summer}
    }
    
    Details
  37. J. Smit and J. A. Huisken, “On the energy complexity of the FFT,” in PATMOS ’95, Postfach 2541, 26015 Oldenburg, 1995, pp. 119–132. [BibTeX]
    @inproceedings{smit95,
      author = {Smit, J. and Huisken, J.A.},
      title = {On the energy complexity of the {FFT}},
      editor = {Piquet, C. and Nebel, W.},
      pages = {119--132},
      booktitle = {PATMOS '95},
      year = {1995},
      organization = {OFFIS},
      publisher = {Bibliotheks- und Informationssystem der
                        Universit\"{a}t Oldenburg},
      address = {Postfach 2541, 26015 Oldenburg},
      note = {ISBN 3-8142-0526-X}
    }
    
    Details
  38. J. A. Huisken, A. Delaruelle, B. Egberts, P. Eeckhout, and J. Van Meerbergen, “Synthesis of synchronous communication hardware in a multiprocessor architecture,” J. VLSI Signal Process. Syst., vol. 6, no. 3, pp. 289–299, Dec. 1993. [BibTeX] [ CrossRef]
    @article{Huisken:1993:SSC:183735.183742,
      author = {Huisken, J. A. and Delaruelle, A. and Egberts, B. and Eeckhout, P. and Van Meerbergen, J.},
      title = {Synthesis of synchronous communication hardware in a
                        multiprocessor architecture},
      journal = {J. VLSI Signal Process. Syst.},
      volume = {6},
      issue = {3},
      month = dec,
      year = {1993},
      issn = {0922-5773},
      pages = {289--299},
      numpages = {11},
      url = {http://dx.doi.org/10.1007/BF01608540},
      doi = {http://dx.doi.org/10.1007/BF01608540},
      acmid = {183742},
      publisher = {Kluwer Academic Publishers},
      address = {Hingham, MA, USA}
    }
    
    Details
  39. J. V. Meerbergen et al., “An integrated automatic design system for compex DSP algorithms,” Journal of VLSI Signal Processing, vol. 1, no. 4, pp. 265–278, Apr. 1990. [BibTeX] [ CrossRef]
    @article{j.90:_dsp,
      author = {Meerbergen, J. Van and Huisken, J. and Lippens, P. and Ardle, O. Mc. and Segers, R. and Goossens, G. and Vanhoof, J. and Lanneer, D. and Catthoor, F. and de Man, H.},
      title = {An integrated automatic design system for compex
                        {DSP} algorithms},
      journal = {Journal of VLSI Signal Processing},
      year = {1990},
      volume = {1},
      number = {4},
      pages = {265--278},
      month = apr,
      doi = {10.1007/BF00929921}
    }
    
    Details
  40. J. A. Huisken, “Efficient design of systems on silicon with PIRAMID,” in Proc. Int. Workshop on Logic and Architectural Synthesis, Grenoble, 1988. [BibTeX]
    @inproceedings{huisken88:effic:piram,
      author = {Huisken, J.A.},
      title = {Efficient design of systems on silicon with
                        {PIRAMID}},
      booktitle = {Proc. Int. Workshop on Logic and Architectural
                        Synthesis},
      year = {1988},
      address = {Grenoble}
    }
    
    Details