My name is Benny Akesson and I am working as Postdoctoral Researcher in the Electronic Systems group in the faculty of Electrical Engineering at the Eindhoven University of Technology. My research is in the area of Real-Time Embedded Systems with interests in resource arbitration, performance virtualization and analysis, power estimation, variability, and design automation. This work is in the system-level context of CompSOC, which is an MPSoC platform for real-time applications with mixed time-criticality. In this context, I lead a team of five people conducting research on Memory Controllers for Real-Time Embedded Systems and developing the CompSOC memory controller and its associated tools.
|Short biography (<50 words)||Long biography (<200 words)|
|2013-05-16 - Article about variation-aware mapping accepted by ACM TECS|
|ACM Transactions on Embedded Computing Systems (TECS) just accepted our article "Process-Variation Aware Mapping of Best-Effort and Real-Time Streaming Applications to MPSoCs". This work discusses how to efficiently map streaming applications, represented as synchronous data-flow graphs, with different types of real-time requirements to multi-processor systems affected by process variation (maximum frequencies of each processor follows a statistical distribution). The main goal is to map the tasks of the applications to the system in such a way that the probability of satisfying the real-time requirements of the applications is maximized. This work is an extension of the conference paper "Process-Variation Aware Mapping of Real-Time Streaming Applications to MPSoCs for Improved Yield", presented at ISQED in 2012.|
|2013-04-17 - Paper accepted at SIES 2013|
A paper entitled "Identifying the Sources of Unpredictability in COTS-based Multicore Systems" was accepted at SIES 2013.
This paper was written together with Dakshina Dasari, Vincent Nelis, Muhammad Ali Awan and Stefan Petters and is the first accepted
paper resulting from the six months I spent at the CISTER-ISEP Research Center in Porto. The contribution of the paper is a survey of sources
of unpredictability in commercial-of-the-shelf multi-core systems and the state-of-the-art research that is addressing them.
Stay tuned for the camera-ready version.
|2013-03-26 - DRAMPower v2.0 released!|
The new version of our tool for fast and accurate system-level power estimation of DRAMs has been released. This version features many important improvements,
such as significantly improved analysis speed (at least 10x), enabling analysis of much larger traces, as well as support for LPDDR/LPDDR2 and Wide I/O memories.
The results of this version have furthermore been verified by Kaiserslautern University of Technology using equivalent circuit-level SPICE simulations,
which established that the error of the tool is < 2% for all memory operations of any granularity for all memories supported by DRAMPower.
For more information, or to download the tool, please refer to the official DRAMPower website.
|2013-02-02 - Paper accepted at DAC 2013|
For the second year in a row, Karthik Chandrasekar lands a paper at the prestigious Design Automation Conference (DAC).
The paper is entitled "Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach" and
discusses how to obtain more realistic power estimates with high-level power models by making them aware of
process variation. Just like his recently accepted DATE paper, this work is a result of a successful collaboration with Christian
Weis and Norbert Wehn at the University of Kaiserslautern.
Update: The paper is now available online. Click here to read it.
|2013-02-01 - Back in Eindhoven|
|After six great months at the CISTER Research Unit in Porto, I am back at Eindhoven University of Technology. I really enjoyed the opportunity to work in another group and learn more about traditional real-time systems and their applications. It has been great to get to know new people in the real-time community, both professionally and as friends. A few papers have already been submitted as a result of this collaboration and there are more to come over the next few months. To all my friends and colleagues in Porto, thank you very much and I look forward to stay in touch with you.|
|2013-01-08 - Jasper Kuijsten graduates from the Memory Team|
|Another master student has graduated from the Memory Team. Jasper Kuijsten joined the team in March 2012 and has worked on predictable and composable reconfiguration of the memory controller front-end. His work has been very diverse and contains theoretical comparisons between different approaches to composability in terms of efficiency and reconfiguration effort, but also implementation of his concepts and ideas in both SystemC and VHDL. The Memory Team thanks Jasper for his hard work and good team spirit during the project and wishes him the best of luck in his future career.|
|2012-10-31 - Memory Team scores four out of four accepted papers at DATE 2013!|
The preliminary author notification for DATE 2013 is now available on the conference
website and it reveals that the memory team scores an incredible four accepted papers
out of the four submitted, resulting in an acceptance ratio of 100% for the team!
The four paper titles are:
|2012-10-31 - Successfull collaboration lands paper at PADL 2013|
|Another successful collaboration has resulted in an accepted publication at the Fifteenth International Symposium on Practical Aspects of Declarative Languages (PADL). The title of the paper is "A Declarative Compositional Timing Analysis for Multicores Using the Latency-Rate Abstraction" and it was written together with Vitor Rodrigues, Simão Melo de Sousa, and Mário Florido from Universidade do Porto and Universidade da Beira Interior. The paper discusses the theory and declarative implementation of timing analysis for multi-cores using abstract interpretation. To manage the state-space explosion of possible interleavings of requests from different cores to shared resources, the latency-rate abstraction is proposed and proven to be sound in the context of the proposed analysis. The resulting loss of precision is then evaluated for a simple system where a memory is shared using TDM arbitration.|
|2012-08-07 - Paper accepted at ESTIMedia 2012|
Andrew Nelson just had a paper "Power Versus Quality Trade-offs for Adaptive Real-Time Applications" accepted at
ESTIMedia 2012. The paper is based on the work of Sjoerd te Pas, one of my graduated master students, and discusses how
power consumption can be traded for application quality for adaptive real-time applications using existing DVFS techniques. The techniques
are demonstrated for an H.263 application on an FPGA instance of the CompSOC platform. Stay tuned for the camera-ready version.
Update: The paper is now available online. Click here to read it.
|2012-08-01 - Visiting researcher at CISTER|
For the next six months, I am a visiting resarcher at CISTER
(Research Centre in Real-Time Computing Systems) based at the School of Engineering (ISEP) of the Polytechnic Institute of Porto (IPP), Portugal.
This gives me a great opportunity to work with some of the great minds in the real-time community, broaden my knowledge by exploring new applications
and research areas, as well as contribute with my experiences to the group. At this point, I am familiarizing myself with the work carried out in the
group and the work plan will be defined during the coming month.
Update: After settling in at CISTER, I am now working on two projects. The first one relates to their work on bus contention analysis, which is a familiar topic with a different twist. The second project is related to implementation and evaluation of scheduling algorithms in the Linux kernel, which is a completely new topic. Of course, I am also still spending time managing the work of the memory team in Eindhoven. Some new, some old, but in the end I am learning many new things both technically and culturally, and I am meeting many extraordinary people.
|2012-07-12 - Tutorial accepted at HiPEAC 2013|
Our tutorial Designing Next-Generation Real-Time Streaming Systems was accepted at HiPEAC 2013,
which takes place in Berlin January 2013. The tutorial is a collaboration between Eindhoven University
of Technology, ST-Ericsson and
Saarland University, and presents, among other things, predictability concepts from the
CompSOC platform and its associated toolchain. We hope to see you there!
The tutorial webpage is available here.
|2012-07-06 - 5th Workshop on Compositional Theory and Technology for Real-Time Embedded Systems|
I have been appointed program co-chair of the on 5th Workshop Compositional Theory and Technology for Real-Time Embedded Systems
(CRTS 2012) together with Bjorn Andersson from the Software Engineering Institute at Carnegie Mellon University, USA. The workshop
is co-located with the Real-Time Systems Symposium (RTSS) in Puerto Rico and takes place on December 4th, 2012.
The goal of the workshop is to reduce the increasing design and analysis cost of real-time embedded systems by proposing
solutions based on compositional platforms and methodologies. These enable decomposition of a complex systems into components that can
be designed and analyzed in isolation and then integrated using interfaces with clearly defined temporal and functional properties.
We gladly invite you to submit contributions to the workshop or to participate during your stay at RTSS.
Click here to visit the workshop website.
|2012-06-21 - Master projects|
It is the time of year when I start getting a lot of questions from master students about opportunities
for master projects, either internally here at the university, or at companies. To streamline the process,
I have created an online form where you can fill out some basic information required to help you
find a suitable project related to my memory controller research, the general CompSOC context, or
maybe something completely different.
The form is available here.
|2012-05-15 - Paper accepted at DSD 2012|
The memory team congratulates Gervin Thomas from TU Berlin for having
his paper entitled "A Predictor-based Power-Saving Policy for DRAM Memories"
accepted at DSD 2012. This work is the result of Gervin's HiPEAC collaboration visit in Eindhoven between
August and October 2011. During this time, he worked closely with Karthik Chandrasekar on finding a way to use
the self-refresh mode of DRAMs to reduce the power consumption in soft real-time systems without significantly reducing
performance. The camera-ready version of the paper will be available shortly.
Update: The paper is now available online. Click here to read it.
|2012-05-15 - Karthik Chandrasekar receives HiPEAC collaboration grant|
|Today we celebrate that Karthik Chandrasekar has received a 3 month HiPEAC collaboration grant to visit the group of Prof. Norbert Wehn at Kaiserslautern Institute of Technology. The application process was competitive with approximately 30% of 67 proposals being funded. The grant serves to extend the existing collaboration between our two groups and will be used to conduct research on the hot topic of "Mobile and 3D-Stacked Wide I/O DRAM Power Modeling and Optimization".|
|2012-05-14 - Spreading the good word|
In 2012 we have continued to spread the good word about the CoMPSoC platform and its real-time memory controller through
a number of invited presentations. The presentation "Composability and Predictability in the CoMPSoC platform" was given
in a one hour version at Research Centre in Real-Time Computing Systems (CISTER) in Porto, Portugal in February and in a three
hour version at Mälardalen Real-Time Research Centre (MRTC) in Västerås, Sweden, last week. The latter presentation was given for
the second year running as an invited lecture in a graduate course on Advanced Real-Time Systems. Last month, our memory controller
work was promoted at Lunds Institute of Technology (LTH) in Lund, Sweden. This visit implied going back to my roots, since this is
the university where I obtained my master degree. This is also the university from which I was sent to Eindhoven in 2004 to start a master project on the topic
of real-time memory controllers, thus taking my first steps towards building a new research area that would keep me and several others entertained for years.
Does the good word need to be spread at your company or institution? Please do not hesitate to contact us.
|2012-05-01 - New PhD student on the memory team|
|The memory team welcomes Yonghui Li who just embarked on the four year quest towards a PhD degree in the context of the T-CREST project. We wish him the best of luck on this endeavor and look forward to working together.|
|2012-03-09 - CoMPSoC website launched - compsoc.eu|
The CoMPSoC project has launched an official website, www.compsoc.eu, with information about
the research, references to key publications, and links to the websites of the individual websites of the researchers. I recommend having a look
at this website, since it shows the system-level context, the bigger picture, of the memory controller research done by the memory team.
Update: The DATE demo is now posted on compsoc.eu for those that were unable to see it in Dresden.
Click here to enjoy the demo.
|2012-02-10 - Paper accepted at DAC 2012|
Today we congratulate Karthik Chandrasekar on getting his paper
"Run-Time Power-Down Strategies for Real-Time SDRAM Memory Controllers"
accepted at Design Automation Conference (DAC) 2012, where it will be presented
in early June. The paper proposes two run-time power down strategies for real-time
SDRAM controllers that reduce power without sacrificing guaranteed bandwidth. One strategy
is conservative and saves power without affecting latency, whereas the second is more aggressive
and saves additional power at a slightly increased latency. The paper also
presents an algorithm to select the most energy-efficient power-down mode at run-time.
Update: The camera-ready version is now available. Click here to download it.