Kees Goossens, Full Professor


As of January 2010, full-time full professor in Real-Time Embedded Systems
in the Electronic Systems group
in the Electrical Engineering faculty
at the Eindhoven University of Technology (TU/e).

The Eindhoven University of Technology is ranked high in university rankings. Again in 2016, it is the best Netherlands university, according to the Times Higher Education Supplement and the fiftieth best university in the world, according to the THES ranking.

The TUE has been number 1 worldwide in collaboration and research with industry for several years running!


  • Fully functional silicon of a three-core CompSOC platform with network on chip!
  • Rasool Tavakoli will soon his thesis. See the publication page for his thesis.
  • Gabriela Breaban successfully defended her thesis. See the publication page for his thesis.
  • Yonghui Li successfully defended his thesis. See the publication page for his thesis.
  • Manil Dev Gomony and Sven Goossens successfully defended their theses. See the publication page for their theses.
  • Karthik Chandrasekar, Pavel Zaykov, Ashkan Beyranvand Nejad, and Andrew Nelson all successfully defended their theses. See the publication page for their theses.
  • We released our RTMemController, an open-source WCET and ACET analysis tool for real-time memory, as published in our ECRTS'14 paper.
  • We received the HiPEAC award for our 2013 DAC paper "Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach".
  • We released a new Version 3.1 of DRAMPower, the Open Source DRAM Power and Energy Estimation Tool.
    The DRAMPower tool performs DRAM command trace analysis based on memory state transitions and hence, avoids cycle-by-cycle evaluation, thus speeding up simulations. The tool supports all basic DRAM memory operations including read, write, refresh, activate, precharge and auto-precharge, besides active and precharged power-down and self-refresh modes. The tool has also been extended to support power estimation of dual-rank DIMMs including IO and Termination power. This feature also enables power estimation of multiple 3D-stacked Wide IO DRAM dies (equivalent to multiple ranks). Finally, the tool also supports variation-aware power estimation, for a selection of DDR3 memories manufactured at 50nm process technology, based on the Monte-Carlo analysis presented in our DAC'13 article. Check it out now at

    Research Topics

  • real-time embedded multi-processor systems
  • memory controllers
  • reducing complexity, e.g. through compositional architectures and analyses
  • low power for real-time applications
  • variability in all its aspects
  • all aspects of networks on chip See the Research and Publication pages for more details.

    Much of this research has been performed as part of national and international research projects. Running projects are: COMP4DRONES DEWI, ENABLE-S3 FITOPTIVIS, HiPER, I-MECH, SCOTT, ZERO .
    Finished projects are: 3DIM3, BENEFIC Cobra, COMCAS EMC2 Flextiles INDEXYS, MESA, NEST, NEVA, OpenES, RESIST, SCALOPES, T-CREST, TSAR.

    All the research is in collaboration with MSc and PhD students, postdocs, Electronics Systems staff, and other researchers at NXP Semiconductors, Delft university of technology, and other (Dutch) universities.

    Other Positions

    Previous Positions

    Previous Research Topics

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