Kees Goossens has a BSc in computer science from the University of
Wales (1988), and a PhD from the University of Edinburgh (1993).  In
his thesis he investigated the formal verification of hardware, in
particular by using semi-automated proof systems in conjunction with
formal semantics of hardware description languages such as ELLA and
VHDL.  He continued this work at several other universities before
joining Philips Research in the Netherlands in 1995.  At Philips he
worked on behavioural synthesis for high-throughput video processing,
then on on-chip communication protocols and memory management.  Until
2010, at Philips/NXP Semiconductors Research he led the team that
defined the Aethereal network on chip for consumer electronics, where
real-time performance and low cost are major constraints.  He was also
part-time full professor at the Delft university of technology from
2007 to 2010, and is currently full professor at the Eindhoven
university of technology, where his research focusses on composable
(virtualised), predictable (real-time), low-power embedded systems,
supporting multiple models of computation.  He was also system
architect at Topic Embedded Products, working on real-time dependable
dynamic partial reconfiguration in FPGAs for two years. He is
editorial board member for the ACM Transactions on Design Automation
of Electronic Systems (TODAES), associate editor for the Springer
Journal of Design Automation of Embedded Systems (DAEM), and was guest
editor for several special issues on networks on chip.  He is author
on 24 patents, and published four books, 175+ articles, with four
paper awards.  His 2003 paper was selected as one of the 30 most
influential papers of 10 years of the DATE conference.  He is or was
steering committee member of ACSD, NOCS, MPSOC, and TPC member of
CODES+ISSS, CRTS, DATE, DSD, ECRTS, FPL, ICPP, INA-OCMC, OMHI, NoCArc,
PARMA, QVVP, ReConFig, RTAS, SAMOS, SDR, SOC, and VLSI-SOC, etc.