DRAMPower is an open source tool for fast and accurate DRAM power and energy estimation for DDR2/DDR3/DDR4, LPDDR/LPDDR2/LPDDR3 and Wide IO DRAM memories based on JEDEC standards. The tool is based on the DRAM power model developed jointly by the Computer Engineering Research Group at TU Delft and the Electronic Systems Group at TU Eindhoven and verified by the Microelectronic System Design Research Group at TU Kaiserslautern with equivalent circuit-level simulations.
The tool can be employed at two levels of abstraction to enable easy integration into existing system design flows: (1) Command-level and (2) Transaction-level. Users employing DRAM memory controllers in their existing system setup can log the DRAM command traces and employ DRAMPower at the command-level. Users without access to DRAM memory controllers can make use of DRAMPower at the transaction-level. To facilitate the same, DRAMPower now includes an optional DRAM command scheduler, which dynamically schedules and logs DRAM commands, corresponding to the incoming memory transactions, as if it were a regular memory controller. It assumes closed-page policy, employs FCFS scheduling across transactions and uses ASAP scheduling for DRAM commands. The generated DRAM command schedule is analyzable for real-time applications.
The DRAMPower tool performs DRAM command trace analysis based on memory state transitions and hence, avoids cycle-by-cycle evaluation, thus speeding up simulations. There are two ways to provide the DRAM command traces: (1) as XML files that are parsed by the tool and (2) compile the tool as a library and call it directly from a simulator using a provided API. The power model and equations have been updated for better accuracy in consultation with TU Kaiserslautern [3]. As a result, DRAMPower is faster and more accurate than similar tools performing cycle-accurate analysis. The tool supports all basic DRAM memory operations including read, write, refresh, activate, precharge and auto-precharge, besides active and precharged power-down and self-refresh modes. The tool has also been extended to support power estimation of dual-rank DIMMs including IO and Termination power (based on Micron's DRAM Power Calculator). This feature also enables power estimation of multiple 3D-stacked Wide IO DRAM dies (equivalent to multiple ranks). The DRAMPower tool has been validated using measurements on actual hardware [4].
Finally, the tool also supports variation-aware power estimation and performance optimization for DDR3 memories, based on the Monte-Carlo analysis presented in our DAC'13 article [5] and the performance characterization algorithm presented in our DATE'14 article [6]. Towards this, 15 sample DDR3 datasheets reflecting the variation-impact on DRAM currents are provided. Also, a test bitfile and the associated source code are provided separately, to optimize performance of DDR3 DIMMs mounted on ML-605 boards.
If you decide to use DRAMPower in your research, please cite one of the following references:
References:
To cite the DRAMPower Tool
[1] DRAMPower: Open-source DRAM Power & Energy Estimation Tool
Karthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens
URL: http://www.drampower.info
To cite the DRAM power model
[2] Improved Power Modeling of DDR SDRAMs
Karthik Chandrasekar, Benny Akesson, and Kees Goossens
In Proc. 14th Euromicro Conference on Digital System Design (DSD), 2011
To cite the 3D-DRAM power model
[3] System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs
Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens
In Proc. Design, Automation and Test in Europe (DATE), 2013
To cite validation of the tool by hardware measurements
[4] High-Level Power Estimation and Optimization of DRAMs
Karthik Chandrasekar
In PhD Dissertation, Delft University of Technology, 2014
To cite variation-aware DRAM power estimation
[5] Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach
Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens
In Proc. Design Automation Conference (DAC), 2013
To cite variation-aware DRAM performance characterization
[6] Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization
Karthik Chandrasekar, Sven Goossens, Christian Weis, Martijn Koedam, Benny Akesson, Norbert Wehn, and Kees Goossens
In Proc. Design, Automation and Test in Europe (DATE), 2014
To cite the bank-wise features PASR and Per-Bank Refresh
[7]A Bank-Wise DRAM Power Model for System Simulations
Deepak M. Mathew, Eder F. Zulian, Subash. Kannoth, Matthias Jung, Christian Weis, Norbert Wehn.
International Conference on High-Performance and Embedded Architectures and Compilers 2016 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), Stockholm, 2017.
To cite the bank-wise DRAM power simulation
[8]A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
Matthias Jung, Deepak M. Mathew, Eder F. Zulian, Christian Weis, Norbert Wehn.
International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016), September, 2016, Bremen, Germany
Licensing:
This tool is released now under the BSD 3-Clause License. This gives the users and developers the flexibility to employ, develop and re-distribute the source code with minimal obligations. We only ask users to cite one of the references listed above.
You may use the software subject to the license terms below provided that you ensure that this notice is replicated unmodified and in its entirety in all distributions of the software, modified or unmodified, in source code or in binary form.
Copyright (c) 2012 TU Delft, TU Eindhoven and TU Kaiserslautern
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
- Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Download:
By clicking the 'Download' (
) button below, you
acknowledge that you have read, understood and accepted to use DRAMPower under
the terms of license detailed above. The current version of the tool is v4.0
and was released on 10th September 2014. Feel free to forward your
questions to Benny Akesson at k.b.akesson@tue.nl.
For intermediate releases or if you want to contribute to the tool,
please check out DRAMPower on github. DRAMPower v4.0 is
also available as a part of the gem5 simulator system.
DRAM Performance Characterization and Optimization:
Documentation:
The following files are also included in the package and have been linked here for quick and direct reference.