The Epicurus program

Ambient Intelligence is the vision that technology will become invisible, embedded in our natural surroundings, present whenever we need it, enabled by simple and effortless interactions, attuned to all our senses, adaptive to users and context and autonomously acting. High quality information and content must be available to any user, anywhere, at any time, and on any device. A typical next-generation embedded multi-media system operating in such an environment is a mobile device that combines high-quality real-time media processing with acceptable usage times between recharges (e.g., mobile phones, gaming devices, pda's). These systems increasingly need high-performance, low-energy compute platforms. The solution is found in multi-processor systems integrating many average-speed and energy-efficient processing elements on a single chip.

Future generations of both heterogeneous and homogeneous single-chip multi-processor systems require novel programming techniques that fully exploit the properties of these systems to guarantee not only functionally correct behavior of an application but also desired timing- and power-related properties. Kahn Process Networks (KPNs) are a good basis for programming multi-processor systems, particularly when aiming at streaming applications where data transformation plays an important role (such as video and graphics processing). KPNs or variants of it are widely used by industry. KPNs have a formal semantics, are fully compositional, and make task-level concurrency explicit. A weak aspect of KPNs is that they are not very suitable for modeling reactive behavior and control, which will play an increaslingly important role in future multi-media applications (such as gaming applications); furthermore, KPNs do not allow explicit reasoning about timing and energy aspects.

An important topic of research in the Epicurus program is to develop a computational-network framework extending KPNs that addresses these issues. We aim at both a sound theoretical framework and a programming environment. Important is the study of analysis techniques that provide insight in concurrency-, timing-, and energy-related properties at the specification level without fully implementing an application.

A second focus is formed by mapping techniques to map specification-level computational networks onto single-chip multi-processor systems. These techniques must optimize execution time, memory usage, and energy usage and allow trade-offs. The result of the mapping is an implementation-level computational network optimized towards the intended multi-processor platform.

Mapping technology builds upon compiler technology that covers the final step from computational-network implementation to the hardware; it concerns the efficient execution of (sequential) code on various sorts of processing elements.

The main research directions of our group in compiler technology are retargetable code generation, reconfigurability, and iterative compilation.

Compilation tools must be easily adaptable to different processing elements. A low cycle count (or high execution speed) is essential to cope with real-time constraints. A low instruction count (or high machine code density) is especially required when the machine code is stored on the chip to achieve low power dissipation and silicon area. Usually different phases in code generation are applied sequentially to ease the compilation work, but the performance is largely affected by the phase coupling. It is our goal to study the integration of these phases in code generation to produce high performance code. We further aim at taking into account as many of the architectural constraints as possible in this integrated framework.

Reconfigurable processing elements are a new type of processing elements that combine a microprocessor core with reconfigurable logic. Our main research goal is to reduce power dissipation by exploiting reconfigurability. An interesting question is how to tune the instruction set and the storage and communication architecture to (part of) the application?

Power consumption and execution time of executable code depends heavily on the source code that is fed into a compiler. Source-code transformations have been developed to reduce power consumption and improve execution time. Research on iterative compilation techniques aims at the development of an automated method to determine which transformations to apply, in which order, and to which sections of code.