The Verilog files produced by the CoCentric SystemC compiler can be imported in FPGA Compiler II. The FPGA compiler can be used to create a netlist file (EDIF format) of our design. In our case the FPGA compiler should result in one file: BENIF_NET.edf, input to the Xilinx ISE software. See the NOC design flow or the FPGA Compiler II User Guide for more information.
The Sysnopsis FPGA Compiler II has been provided in the context of the Synopsis University Program.
The FPGA Compiler II has to be installed on Windows NT (2000, XP). The installation also requires access to a license file or server. Users at the the ICS group of the Electrical Engineering Department of the Technische Universiteit Eindhoven can use the license server o3.ics.ele.tue.nl.
Fill in the installation options as shown in the following message boxes:
See the NOC design flow or the FPGA Compiler II User Guide for more information.