The design flow for the mMIPS NOC (figure 1) on this page
describes the steps necessary to
create a hardware simulator
(C) or to
create a FPGA implementation
(D) starting with the SystemC sources
of the NOC. Creating a hardware simulator is easy and fast when
compared to the process of creating a FPGA implementation. The
disadvantage of the hardware simulator
is that is typically one or twenty thousand times slower than the actual
implementation. Only students that
have access to the servers of ICS/ES and the tools described in the
package can actually perform the steps; for others they are merely a
good indication of the design flow.
The Sysnopsis tools in the flow of figure 1 have been provided in the context of the Synopsis University Program.
This section describes the procedure to create a simulator of the
mMIPS NOC based on its SytemC/C++ sources.
This section describes the steps in the design flow from SytemC/C++
sources of the mMIPS NOC to its FPGA implementation.
1. Synopsys SystemC compiler (SystemC =>
Verilog)
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The SystemC sources for the mMIPS
NOC are in ./noc/mips and
./noc/ecube and the subfolders. We use the
Synopsys CoCentric SystemC compiler
which is installed on the ICS servers
to create a Verilog version of our NOC implementation. Each
SystemC module (declared as SC_MODULE(module_name)) is
translated into a separate Verilog module and placed in a
module_name.v file. These files serve as the input for the
Synopsys FPGA Compiler II.
- Connect to an ICS Server
Since the SystemC libraries are on the servers of ICS, you need to log on
to on of them (e.g. co7.ics.ele.tue.nl) first. If you are using Windows
you can use a SSH
(Secure Shell) client such as SSH Secure Client to log on (instructions). Use
the Extended C Shell called tcsh. Since
this is the default logon shell for new user accounts, you should already
be using it. Type
ps -a (which gives a list of running
processes) to see if it is running. If it is, the list returned by
ps should include tcsh. If not, start it
by typing tcsh.
- Verify SystemC environment
The tcsh environment should contain
information on the whereabouts of SystemC and a special SystemC script
should have run. We have to check if all that is the case. Use the command
env to show all environment variables and
verify that these are among them: LD_LIBRARY_PATH, SYNOPSYS, SYNOPSYS_CCSS.
If any of them is not among them, then the environment is probably not set
up correctly at logon. The file
.cshrc in the root of your home directory (/home/<your_user_name>)
is executed whenever a user or script enters the
tcsh and should contain a line with the text
"source ~/synopsys.env". If this is not
the case add it and copy the file
./samples/synopsys.env to the root of your
home directory and add the aforementioned command to
.cshrc (create the file if it does not
exist). Log out and log on and verify that the environment is now
set up correctly.
- Compile the NOC sources
The SystemC sources for the mMIPS
NOC are in ./noc/mips and
./noc/ecube and its subfolders, but the
script
systemc_2_verilog which is used to convert them
to Verilog is in ./noc/cocentric. Run the
script. It stores
the resulting Verilog files in the same directory. Assuming that you
haven't changed the sources, the resulting Verilog files should be the
same as the ones in
./samples/noc/verilog. If you encounter
compilation problems, try to compile the sources that came with the
package. If this also doesn't work, you may need to use another version of
gcc. Synopsys SystemC compiler requires gcc version 2.95.3 for its
preprocessing. You can
check what your g++ "points to" by typing
which g++ and g++
--version to determine its version. If you are using a different
version, you have to change the aforementioned Makefiles. Include a full
path to the correct version.
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2. Synopsys FPGA Compiler II (Verilog
=> Netlist (EDIF))
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The Verilog files from the SystemC compiler are the input for a new project in FPGA Compiler II. The resulting file
from this project should be a netlist in EDIF format called BENIF_NET.edf.
- Install Synopsys FPGA Compiler II
The FPGA Compiler II needs to be installed on a PC with Windows 2000 or up
(installation
instructions).
- Copy Verilog files
Use the SSH Secure Client copy the files from the ICS server to the
computer with FPGA Compiler II (transfer
instructions).
- Start Compiler
Start the Synopsys FPGA Compiler II and create a new project without the "DesignWizard".
- Add source files
Create a new folder to hold your project files. You will be asked for the
source files. Select all Verilog sources that you created with the SystemC
compiler. Note that these files are not copied to the project directory.
- Select top level design
You will now return to the main window of the compiler and verification of
all sources will start automatically. Once this process has completed
successfully, select BENIF_NET as the top level design from the drop down list in
the toolbar of the main FPGA Compiler II window.
- Create implementation
The "Create implementation" dialog box should appear.
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Figure 2: Top level view of
the NOC in the FPGA |
Enter the target device properties (see figure 2) as follows:
Vendor: |
Xilinx |
Family: |
Virtex2 |
Device: |
2V3000FG676 |
Speed grade: |
-4 |
Important: Since BENIF_NET
is not connected directly to the I/O pads of the Xilinx Virtex2 FPGA (see
NOC implementation overview), we have to check "Do not insert I/O
pads". If desired the optimization constraints or output options
can be changed, but the values shown above should be sufficient.
Cllick OK to start the compiler.
- Export Netlist
When the compilation has finished there should be two chips BENIF_NET and
BENIF_NET-Optimized (see figure 3).
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Figure 3: The
implementations generated by the FPGA compiler |
Right click on BENIF_NET-Optimized and choose "Export netlist...".
Uncheck "Export Timing Specification" in the dialog box that appears
(figure 4). Save the netlist.
- The netlist will saved as "BENIF_NET.edf".
The BENIF_NET.edf that should result from
compiling the Verilog files for the NOC that comes with the package is in
./samples/noc/netlist.
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3. Xilinx ISE (Netlist =>
bitfile)
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The Xilinx ISE software is used to create a bitfile that
can be used to program the FPGA. Xilinx ISE uses (among other things) the netlist
BENIF_NET.edf that was created using the
FPGA Compiler II in the previous step.
The ISE
software has to be installed on a PC with Windows 2000 or newer. ICS has
only a few licenses for this software so you need find a computer with this
software. The steps to create a bitfile using
Xilinx ISE are as follows:
- Copy Xilinx project files
An ISE project named bennoc has been set up in the directory ./noc/bennoc
of the package. Copy this directory to the computer that has Xilinx ISE
installed. Then copy or move the netlist of the BENIF_NET module that was
created with FPGA Compiler II to
./noc/bennoc/noc. The
other directory, ./noc/bennoc/commcore,
contains the VHDL sources for the Comm.Core module (benif_32reg_24bmem)
that functions as an interface between BENIF_NET and the pins on the FPGA
(see NOC implementation overview for
more info). The directory ./noc/bennoc
contains bennoc.vhd which
instantiates and connects the two the communication core module
Comm.Core and BENIF_NET. The file
benone_benadda3000fg676.ucf associates ports of the design with
appropriate pins of the User FPGA. All files necessary for the project are
shown in table 1.Table 1: Files used for the project Xilinx ISE project.
Directory/file | description |
./noc/bennoc |
Top-level project directory for the Xilinx ISE project "bennoc". |
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bennoc.npl | Xilinx ISE Project
information (needed for Xilinx Project Navigator). |
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bennoc.vhd | Top-level project module
which connects Comm.Core and BENIF_NET. |
•
benone_benadda3000fg676.ucf | Pin assignment
for the Xilinx Virtex2 FPGA on the BenOne development board. |
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./noc/bennoc/noc | SystemC design directory. |
- BENIF_NET.edf | EDIF description of the
synthesized Network-on-FPGA (from FPGA Compiler). |
•
./noc/bennoc/commcore |
Nallatech communication core Comm.Core. |
- commcore.vhd | Instantiation of a single communication module
(benif_32reg_24bmem). |
- sv_iface.vhd | Top-level communication core generic. |
- if_main.vhd | Spartan-Virtex interface. |
- dma_ctrl.vhd | DMA controller. |
- fwfrff_32.vhd | DMA controller's FIFO. |
- fifocnt4.vhd | FIFO counter. |
- rm16x32d.ngc | Precompiled memory core implementing FIFO's memory. |
- Open Xilinx Project Navigator
Start the Xilinx Project Navigator (part of Xilinx ISE) by double clicking
on ./noc/bennoc/bennoc.npl.
- Generate a programming file
Generate a programming file by selecting the file
bennoc.vhd (in the plane named "Sources in Project:") and then
right clicking on "Generate Programming File" (in the plane
named "Processes for Current Source:") and
choosing "Run" (see figure 5). When the programming process has completed
you can close Xilinx Project Navigator and there should be a bitfile called bennoc.bit
in the root of the project structure (./noc/bennoc).
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Figure 5: Xilinx Project
Navigator with the bennoc project. |
- Program the FPGA
The program bendime.exe can be used to copy
bennoc.bit to the FPGA (see next step).
The
bennoc.bit that should result from the the
netlist BENIF_NET.edf that comes with the
package is in ./samples/noc/bitfile. Of
course you also need to upload one of the example applications before you
can actually test the mMIPS NOC. See the
application design flow to see how to compile such a program for the
FPGA.
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The program
bendime.exe can be used to upload the bitfile with the mMIPS NOC
and the applications (e.g. gossip) to the FPGA, start the processors and
retrieve the resulting memories. bendime.exe
requires the Nallatech FUSE software and of course a connected development
board. The batch file bennoc.bat in ./noc/bendime
can be used to upload bennoc.bit and the
memories for the processors (mips_rom.xXyY.bin and mips_rom.xXyY.bin) to the
FPGA, start the processors and retrieve the resulting memories (mips_ram.xXyY.dump).
The script is for a 2-by-2 mMIPS NOC and so (X,Y) is (0,0), (1,0), (0,1) or
(1,1). The batch file assumes that these memories,
bennoc.bit and bendime.exe are in the
same directory. If there is a working NOC on the FPGA, then you can save
time by skipping the upload of the bitfile by using benapp.bat
instead of bennoc.bat. |