The Network-on-chip (NOC) that comes with the package consists of four mMIPS processors connected using a torus network with E-cube routing. The implementation of the NOC is in C++ using the SystemC libraries; the example applications have been written in C. The sources of the NOC and the example applications are for a 2-by-2 (4 nodes) variant of the NOC, but it is possible to change the size of the network. The NOC has been tested extensively using the complex multi-processor JPEG decoder.
The NOC itself cannot be placed on a FPGA, because it lacks an interface to the outside world. The user needs such an interface for things like starting the processors and uploading or retrieving their memories. Two extra modules provide this interface. The first module, Comm.Core, is connected to the pins of the FPGA on one side and to the second module on the other. The Comm.Core module implements a register or DMA based communication scheme. The second module, BENIF_NET_WRAPPER, uses the register communication scheme of Comm.Core. Register addresses and their data have special meanings to the BENIF_NET_WRAPPER module and can be used for the desired processor control functionality and memory access.
Figure 1 shows our NOC and the interface modules as they appear on the FPGA of the BenOne development board.
Figure 1: Top level view of the contents of the FPGA with the NOC and extra modules.
The list below gives a short description of components discussed earlier and in figure 1.
|•||Comm.Core||-||The Comm.Core is supplied by development board manufacturer Nallatech. It provides a register or DMA based communication scheme between the a PC that runs Nallatech's FUSE software on the one side and the interface module BENIF_NET_WRAPPER of our design BENIF_NET on the other side.|
|•||BENIF_NET||-||This is the top level module which encapsulates our mMIPS NOC including its interface to the Comm.Core of Nallatech, BENIF_NET_WRAPPER. All these sources are in SystemC.|
|▫ dp_xXy||-||The four mMIPS processors with their network interfaces are instantiated as dp_x0y0, dp_x1y0, dp_x0y1 and dp_x1y1 (dp stands for "data processor"). The name of these modules in the SystemC sources is NETmMIPS.|
|▫ NETWORK2x2||-||The module NETWORK2x2 encapsulates the routers that interconnect the network interfaces of the mMIPS processors.|
|▫ BENIF_NET_WRAPPER||-||The BENIF_NET_WRAPPER is the interface to the Comm.Core of Nallatech. The wrapper gives special meanings to the register addresses and data used in the the Comm.Core to make the mMIPS processors and their memories available for reading and writing and to optionally start or stop them.|
Go to the NOC design flow to find out how to generate the NOC on FPGA starting form the SystemC sources.