Advanced Computer Architecture

Course year: 2007-2008

Code :	5MD00 (3 ECTS) / 5Z033 (4 ECTS)
Lecturers :	Prof. dr. Henk Corporaal Prof. dr. ir. R.H.J.M. Otten
Email :	H.Corporaal at tue.nl
Phone :	TU/e: +31-40-247 5195 or 3653 (secr. TU/e) / 5462 (office TU/e)
Assistance:	Dr. ir. Sander Stuijk (miniMIPS models + FPGA synthesis): s.stuijk at tue.nl Ir. Akash Kumar (FPGA synthesis, LCC compiler): a.kumar at tue.nl Dr. ir. Bart Theelen (miniNOC): B.D.Theelen at tue.nl
Prerequisets:	Course in computer architecture and processor design; e.g. Processor Design 5Z032 or Computation 5JJ70; Programming experience in C, C++, or equivalent language

Description and objectives

Studying the architecture, organization and use of the newest (micro)processors currently on the market, and the latest research developments in computer architecture. Architectures exploiting instruction-level parallelism (ILP) and task-level parallelism are treated. Starting from basic architecture concepts we will end with discussing the latest commercial processors (e.g., Pentium 4 multi-core, EPIC processors like Itanium, and embedded processors such as the TriMedia), and academic processors (like TRIPS).
This course also treats how processors can be combined in a multiprocessing platform, e.g. by using a Network-on-Chip. Interprocessor communication issues will be dealt with. Furthermore new code generation techniques needed for exploiting ILP will be treated. Special emphasis will be on quantifying design decisions in terms of performance and cost.

The intention of the course is to give students the ability to understand the design principles and operation of new (multi-)processor architectures, and evaluate them both qualitatively and quantitatively. Although we treat several examples, the emphasis will be on architecture concepts. Furthermore, the aim is to design, implement and test a Network-on-Chip, by one or more student teams.

Topics:

Basic principles (like instruction set design), pipelining and its consequences; VLIW (very long instruction word) architectures, Superpipelined, Superscalar, SIMD (single instruction, multiple data, used in vector and sub-wordparallel processors) and MIMD (multiple instruction, multiple data) architectures; Embedded architectures; Out-of-order and speculative execution; Branch prediction; Data (value) prediction; Design of advanced memory hierarchies; Memory coherency and consistency; Multi-threading; Exploiting task-level and instruction-level parallelism; Inter-processor communication models; Input and output; Network Communication Architecture; and Networks-on-Chip.

Book and Handouts

Computer Architecture: A Quantitative Approach; 4th ed.

John L. Hennessy and David A. Patterson
Morgan Kaufmann Publishers
ISBN 1-55860-724-2 or 1-55860-596-7

Handouts (for slides see below):

Trends in programmable instruction-set processor architectures Chapter 2 of book Microprocessor Architectures: from VLIW to TTA.
Techreport on A layered MIMD Communication Processor Design and Classification model.

Slides

** will be added and updated during the course period **

Overview slides (including preliminary schedule)
Lecture 1: Computer Systems Overview
Lecture 2 + 3: Crash course on MIPS

MIPS instruction set
MIPS design 1: single cycle and multi-cycle implementations
MIPS design 2: pipelined implementation

Lecture 4: Instruction-set design
Lecture 5: Instruction-Level Parallel (ILP) architectures

Other architectures

Lecture 6: Exploiting ILP with Software approaches
Lecture 7: SMT: simultaneous multi-threading
Lecture 8: Multi-Processors and Interconnection networks;
Including Synchronization, Coherence, and Consistency
Lecture 9: Lab project

Lecture 10: Caches and Memory Hierarchy;
Many techniques to speed up this memory hierarchy

Project

Part of the course will be project based. In this project the students will program and modify an advanced processor network, using SystemC as implementation language and, optional, FPGA as realization target technology. Students will work in a group of 2 people to perform this project. At the end each group has to write an report about the lab. assignments and prepare a short (slide) presentation; clearly indicate the individual contributions of both group members.
The results of the first two lab. assignments have to be demonstrated per group (a date will be determined for that).

The project contains three laboratory assignments.

Study the slides mini Network-on-Chip on FPGA
Study the material on our mini Network-on-Chip site
See project slides for details on the project.

Examination

The examination will likely be oral.
The grade is based on your project results (and being able to explain and defend them) and the discussed theory (study all slides, book chapters and handouts).