Platform-based Design

2007 - 2008 (1st semester)mica2dot

Code : 5KK70
Credits: 5 ECTS
Lecturers : Dr. Bart Mesman, Prof. dr. Henk Corporaal
Tel. : +31-40-247 5195 / 3653 (secr.) 5462 (office)
Email:  B.Mesman at; H.Corporaal at
Project assistance: Hamed Fatemi (H.Fatemi at, Akash Kumar (A.Kumarat


Information on the course:


When looking at future embedded systems and their design, especially (but not exclusively) in the multi-media domain, we observe several problems: In order to solve these problems we foresee the use of programmable multi-processor platforms, having an advanced memory hierarchy, this together with an advanced design trajectory. These platforms may contain different processors, ranging from general purpose processors, to processors which are highly tuned for a specific application or application domain. This course treats several processor architectures, shows how to program and generate (compile) code for them, and compares their efficiency in terms of cost, power and performance. Furthermore the tuning of processor architectures is treated. 

Several advanced Multi-Processor Platforms, combining discussed processors, are treated. A set of lab exercises complements the course.

This course aims at getting an understanding of the processor architectures which will be used in future multi-processor platforms, including their memory hierarchy, especially for the embedded domain. Treated processors range from general purpose to highly optimized ones. Tradeoffs will be made between performance, flexibility, programmability, energy consumption and cost. It will be shown how to tune processors in various ways.

Furthermore this course looks into the required design trajectory, concentrating on code generation, scheduling, and on efficient data management (exploiting the advanced memory hierarchy) for high performance and low power. The student will learn how to apply a methodology for a step-wise (source code) transformation and mapping trajectory, going from an initial specification to an efficient and highly tuned implementation on a particular platform. The final implementation can be an order of magnitude more efficient in terms of cost, power, and performance.


In this course we treat different processor architectures: DSP (digital signal processors), VLIWs (very long instruction word, including Transport Triggered Architectures), ASIPs (application specific processors), and highly tuned, weakly programmable processors. In all cases it is shown how to program these architectures. Code generation techniques, especially for VLIWs, are treated, including methods to optimize code at source or assembly level. Furthermore the design of advanced data and instruction memory hierarchies will be detailed. A methodology is discussed for the efficient use of the data memory hierarchy.
Most of the topics will be supplemented by hands-on exercises.
For more information on course and lecture schedule see: course description


The lecture slides will be made available during the course; see also below.
Papers and other reading material

Slides (per topic; see also the course description)

Slides as far as available (will be updated regularly during the course).

Student presentations guidelines

The last two lectures will be used to let you present a topic highly related to this course.
Guidelines are as follows:

Hands-on lab work

Will be updated during the course!

During the course there are three lab exercises to be made (so called hands-on); see also the links below. They will be explained at the corresonding lectures. 

Hands-on 1: Processor Design Space Exploratoin, based on the Imagine architecture

In this excercise we explore the Imagine processor from Stanford University; see the imagine website for details about this processor.
Imagine is a streaming oriented processor. It contains in its basic realization 8 PEs (processing elements) acting in SIMD mode (i.e. each PE executes the same instruction from an instruction controler). The PEs themselves are VLIW type of processors, capable of performing multiple operations per cycle.
For this excercise

Hands-on 2: Platform Programming

In this lab you are asked to program a multi-processor platform.
There are two options: using the CELL platform or using the Wica platform. The first assignment is ready, we are
still working on the second one. So if you want to start today, choose the CELL option.

a. Programming the CELL Broadband Engine

The CELL contains a PowerPC processor and 8 SPEs (Synergetic Processing Engines) of which you can use 6 (number 7 is used by the operating system and number 8 is not guaranteed to be functional). The CELL processor is part of the Sony Playstation 3, which we will use as target. But also a good simulator and compiler environment is available.
All details about the architecture, the simulation and compiler environment, and example programs can be found at the CELL-assignemnt page. Read this page carefully and follow the instructions.

b. Programming the WiCa 1.1 board

The WiCa 1.1 board is developed by Philips and NXP. The board is meant for being used in Smart Camera's. It contains among others the Xetal SIMD image processing chip, containing 320 Processing Elements, and an 8051 microcontroler. To observe the world it contains two image sensors; this allows even for stereo vision and depth calculation.
To connect to your PC it has an USB interface, but you can also attach a ZigBee low power interface to make a smart wireless sensor network.
The assignment is on using the image sensors to detect simple objects, their movement, and if possible, cooperate with other boards.
All details about the WiCa platform, the simulation and compiler environment, and example programs can be found at the WiCa-assignemnt page. Read this page carefully and follow the instructions.

Hands-on 3: Exploiting the data memory hierarchy for high performance and low power

In this exercise you are asked to optimize a C algorithm by using the discussed data management techniques. This should result into an implementation which shows a much improved memory behavior. This improves performance and energy consumption. In this exercise we mainly concentrate on reducing energy consumption. You need to download the following, and follow the instructions:


The examination will be oral about the treated course theory, and the lab report(s).
Date: ** to be decided **.

Related material and other links

Interesting processor architectures:

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