Processor Design

Code : 5Z032
Lecturer : Prof. dr. Henk Corporaal
Tel. : +31-40-247 5195 / 3653 (secr.) 5462 (office)
Email:  H.Corporaal at
Assistance: All on 9th floor:
-- Ir. Akash Kumar (FPGA synthesis, LCC compiler): a.kumar at
-- Dr. ir. Sander Stuijk (SystemC and MIPS models): s.stuijk at


Information on the course:

Description and objectives

The course treats both the architecture and implementation of current RISC type of processors. RISC processors have a reduced instruction-set which enables the pipelined execution of instructions. This gives them a very high instruction throughput and performance, while their implementation is not too complex. RISC processors are used everywhere, not only in general purpose processors (although a Pentium is not a RISC its core also obeys the RISC design principles), but also in billions of embedded systems. This course not only treats how to design these processors, but also details the required memory hierarchy, interfacing, input and output peripherals, and the role of the operating system. In total this gives a thorough understanding of a complete processor system. Part of the course consists of laboratory assignments, where students have to exercise assembly level programming, and implement (parts of) a RISC processor in SystemC. The implementation has to be verified with real programs. The MIPS architecture is used as guiding example throughout the course.

The objectives of this course are: 1) to learn the design principles of different processor architectures, and how they act as target for a compiler (for languages like C); 2) to get a detailed understanding of RISC design principles; 3) learn how to program RISC type of processors; 4) learn different implementations of the same architecture; 5) be able to realize an implementation (at register transfer / signal level) using a HDL (hardware description language); 6) know how a processor fits together with the memory hierarchy, interfaces and operating system, to form a complete processor system, and 7) being able to analyse the performance of a processor system.

Book and Handouts

4th edition
Computer Organization and Design
- The Hardware/Software Interface
4th Edition

David A. Patterson and John L. Hennessy
Morgan Kaufmann Publishers

For the operating systems part you have to download and study the os-sylabus:
Introduction to Operating Systems by
Ben Juurlink (TUD) and Henk Corporaal (TUE).


Lab exercises

Below the details of the required lab-assignments are described. You have to deliver a report describing the results of all assignements, and if asked for during the examination, demonstrate your code and results.

A. MIPS assembly programming exercise

In this exercise we use the SPIM simulator to program the MIPS processor in assembly language. See the home page of the SPIM simulator (for MIPS R2000/R3000 architectures). You are asked to make and demonstrate a program implementing an interesting algorithm which at least contains either a non-leaf function and/or a recursive function. Give both the C-code and assembly code of your program.

B. Design and implementation of an embedded RISC processor

For this exercise we use a small MIPS processor:
This processor is described in SystemC, a language in which you can both describe hardware and software. See Study the user manual of SystemC which you can find on this website, especially the example in chapter two. This exercise contains 3 assignments, as described below.
For full instructions go to MIPS Lab exercises. We will be using a synthasizable SystemC model of the pipelined mini MIPS processor (mMIPS) and the software described in "Software mMIPS-lab". You should install this software on your notebook before your start this assignment.

The objective of this assignment is to familiarize yourself with:

This assignment consists of two parts. In the first part, you will be studying the LCC compiler. This compiler can be used to compile C programs for the mMIPS. In the second part, you will extend the mMIPS model with forwarding logic.

The objective of this assignment is to familiarize yourself with:

This assignment consists of three parts. In the first part, you will be studying the synthesis trajectory which is used to implement the mMIPS on an FPGA. In the second part, you will optimize the design of the mMIPS. The objective is to increase the clock-frequency of the mMIPS. In the third part, you will implement the mMIPS on an FPGA board.

The goal of this assignment is to achieve the fastest execution for a given C-coded algorithm.

In this assignment you have to increase the performance of an image processing algorithm running on the mMIPS processor.  This can be done by making changes to the hardware architecture and/or the LCC compiler.


The examination will be oral; date to be determined.

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