Literature overview considering Instruction Level Parallel Architectures and Code Generation

Henk Corporaal

March 1998

 
• Compiler: general
• ILP architectures: general
• Limits on ILP
• Branch prediction techniques (control prediction)
• Scheduling
• Register Allocation and Register file design
• Speculative execution
• Cache and Memory
• Instruction set issues (mainly for VLIWs)
• Multi-threaded ILP architectures
• Miscellaneous topics
• References
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