Photo Théo

Théodore Marescaux

Mapping and Management of Communication Services

on MP-SoC Platforms

1. Introduction

MP-SoC platforms are becoming very important in nowadays products and their predominance in the portable embedded market is expected to raise. There are multiple reasons why the importance of MP-SoC is increasing:
  1. Reduce non-recurring engineering costs by reusing existing IPs (memories, I/O, processing elements).
  2. Reduce non-recurring engineering costs by designing scalability into the communication architecture. Different product lines can be thus based on the same platform making feature addition a deterministic limited-cost process.
  3. Memory bandwidth is becoming a problem. Distributed (shared) memory is a way to work around this bottleneck.
  4. To follow the dramatic increase in the amount of required compute-power in energy-conservative environment, parallelism is required.
The communication architecture of an multi-processor system-on-chip is the glue that ties together PEs, memory and I/O. Furthermore it should connect them in a consistent, deterministic manner to ease programmability, in-site debugging and thus reduce furthermore non-recurring engineering costs.

MP-SoC communication architectures are meant to provide support to the application and should therefore be tuned to its requirements. In this work, we are considering two common, but quite different, views on application programming: a hardware-oriented, distributed-memory view of the platform from the reconfigurable computing angle and a more mainstream software-oriented (distributed) shared memory view from the multi-processor world.

2. PART I: Flexible Distributed Memory MP-SoC Platforms

In this first part we consider a distributed-memory heterogeneous multiprocessor platform that contains both programmable PEs and fine-grain reconfigurable hardware tiles allowing the implementation of flexible hardware accelerators. This platform is well suited to applications developed with high-level HW/SW co-design languages that assume distributed memory. The communication architecture of this MP-SoC platform is based on an ensemble of Networks-on-Chip (NoC) allowing independent transfer of data and control information. These NoCs are enhanced with distributed controllers that allow monitoring and control of the communication at run-time under the supervision of a central platform controller. Traffic shaping and adaptive re-routing techniques are used to control communication and handle task migration between heterogeneous processors at run-time (FIXME: Link to Vincent).

NoC and NoC control prototype
Distributed Memory MP-SoC prototype that demonstrates NoC communication and run-time NoC management.

3. PART II: High-Level Communication Services and Communication Management of Distributed Shared Memory MP-SoC Platforms

In the second part we consider distributed shared-memory MP-SoC platforms for which the communication patterns of applications can be extensively analyzed at design-time to improve run-time decisions. These design-time techniques use software controlled scratch-pad memories to optimize memory footprint or energy by controlling allocation of arrays to the memory hierarchy and by controlling data communication. To benefit from the gains obtained by design-time application exploration, the communication architecture has to fulfill a number of requirements:
  1. Provide a shared-memory view of a platform that has physically distributed memory.
  2. Provide high-level communication services to allow control of scratch-pad memories.
  3. Provide software-like synchronization primitives (eg. semaphores, barriers, ...) on top of a switched communication architecture.
  4. Provide guarantees on the communication latency and bandwidth in order to guarantee that design-time decisions are enforced.
The fulfillment of these requirements raises a number of research questions that we attempt to address:
  1. Identify and refine the high-level services required by the design-time mapping technique to perform optimal software-controlled scratch-pad management.
  2. Optimize the mapping of the high-level services onto the communication services provided by a QoS-enabled Network-on-Chip
  3. Perform optimal run-time management of the communication resources of the platform and interface with the run-time platform controller (FIXME: Link Vincent),
  4. Optimize the low-level communication infrastructure (the NoC) for the required set of high-level services and guarantees.

Optimal Mapping and Management of MP-SoC communication services 


[1] V. Nollet, T. Marescaux, D. Verkest, J-Y. Mignolet, and S. Vernalde. Operating System controlled Network-on-Chip. In Proceedings of the Design Automation Conference (DAC04), pages 256-259, June 2004. San Diego.
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[2] T.A. Bartic, D. Desmet, J-Y. Mignolet, T. Marescaux, D. Verkest, S. Vernalde, R. Lauwereins, J. Miller, and F. Robert. Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation. In Field Programmable Logic and Application, volume 3203/2004 of Lecture Notes in Computer Science, pages 637-647. Springer Berlin / Heidelberg, 2004.
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[3] T.A. Bartic, J.-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, and R. Lauwereins. Topology adaptive network-on-chip design and implementation. In Computers and Digital Techniques, IEE Proceedings, volume 152, pages 467- 472, July 2005.
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[4] T.A. Bartic, J.-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, and R. Lauwereins. Highly scalable network on chip for reconfigurable systems. In System-on-Chip, 2003. Proceedings. International Symposium on, pages 79- 82, 2003.
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[5] Theodore Marescaux, Andrei Bartic, Dideriek Verkest, Serge Vernalde, and Rudy Lauwereins. Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs. In Field-Programmable Logic and Applications. Reconfigurable Computing Is Going Mainstream 12th International Conference, FPL 2002, Montpellier, France September 2-4, 2002. Proceedings, volume 2438/2002 of Lecture Notes in Computer Science, pages 795-804. Springer Berlin / Heidelberg, 2002.
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[6] Theodore Marescaux, Benjamin Bricke, Peter Debacker, Vincent Nollet Nollet, and Henk Corporaal. Dynamic Time-Slot Allocation for QoS Enabled Networks on Chip. In Proc. IEEE 3rd Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), pages 47-52, New York, USA, 09 2005. IEEE.
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[7] T. Marescaux, J-Y. Mignolet, A. Bartic, W. Moffat, D. Verkest, S. Vernalde, and R. Lauwereins. Networks on Chip as Hardware Components of an OS for Reconfigurable Systems. In Field-Programmable Logic and Applications, volume 2778/2003 of Lecture Notes in Computer Science, pages 595-605. Springer Berlin / Heidelberg, 2003.
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[8] T. Marescaux, V. Nollet, J.-Y. Mignolet, A. Bartic, W. Moffat, P. Avasare, P. Coene, D. Verkest, S. Vernalde, and R. Lauwereins. Run-time support for heterogeneous multitasking on reconfigurable SoCs. Integr. VLSI J., 38(1):107-130, 2004.
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[9] Theodore Marescaux, Anders Rångevall, Vincent Nollet, Andrei Bartic, and Henk Corporaal. Distributed congestion control for packet switched networks on chip. In Parallel Computing Conference (ParCo 2005), Proceedings, Malagà, Spain, 09 2005.
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[10] V. Nollet, T. Marescaux, P. Avasare, and J-Y. Mignolet. Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles. In DATE '05: Proceedings of the conference on Design, Automation and Test in Europe, pages 234-239, Washington, DC, USA, 2005. IEEE Computer Society.
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