Andrei Terechko
Clustered VLIW architectures: ISA, instruction scheduling, and physical
characterization
Abstract:
Ongoing increase of wire delay relative to logic delay in future IC technologies
forces clustering of ILP processors. Clustering breaks the processor core into
clusters of function units and register files. Communication between clusters is
pipelined, which allows for higher the clock frequency. My research focuses on
choosing the efficient ISA architecture for clustered VLIW processors.
Furthermore, I'm developing new instruction scheduling techniques for VLIWs,
and, finally, I plan to characterize the physical advantage of clustering in
terms of clock period, power, and area.