• 5LIH0: Assignment videos illustrating custom digital CMOS design layout with spice simulation, design rule checking (DRC), parasitic extraction (PEX) and logic versus schematic (LVS) verification.

  • 5LID0: Assignment videos illustrating CMOS synthesis, place and route.

  • 5SIB0: Assignment 2: CMOS Synthesis, Place and Route.


Master assignments and internships

We have Brainwave related assignments available:

In the area of error resilience and fault tolerance (Design for Error Resilience: DfER):

More generic VLSI oriented, but directly applicable in Brainwave:

In the area of wireless communication we have the following assignments (some are internships):

Many systems have the need for multiple antenna and direction of arrival. For the linear equation need to be solved. I believe you can do this with very performance using CORDICs:




Jos’ Blog, mostly private notes.