Courses

• 5LIH0: Assignment videos illustrating custom digital CMOS design layout with spice simulation, design rule checking (DRC), parasitic extraction (PEX) and logic versus schematic (LVS) verification.

• 5LID0: Assignment videos illustrating CMOS synthesis, place and route.

• 5SIB0: Assignment 2: CMOS Synthesis, Place and Route.

Assignments

Master assignments and internships

We have Brainwave related assignments available:

• Energy efficient mapping of EEG feature extraction algorithms
• PCB design and evaluation of 8-channel EEG readout system (internship)
• EEG analysis using CNNs

In the area of error resilience and fault tolerance (Design for Error Resilience: DfER):

• Error Injection and Stability Analysis of Digital Processing Architectures
• Error-Resilient Finite State Machines

More generic VLSI oriented, but directly applicable in Brainwave:

• Standard cell library for subthreshold FDSOI 28nm CMOS
• Flipflops with programmable negative setup times

In the area of wireless communication we have the following assignments (some are internships):

• Design and evaluation of different FFT computation architectures
• Design and Evaluation of WIFI Analog Front End using of-the-shelf discrete components
• Energy efficicient design of Time Slotted Channel Hopping
• Virtual wireless communication channel on FPGA

Many systems have the need for multiple antenna and direction of arrival. For the linear equation need to be solved. I believe you can do this with very performance using CORDICs:

• QRD and SVD using fixed point CORDICs

Ongoing

• Brain Computer Interface for locked-in patients started
• SRAM module generator for a 28nm FDSOI CMOS process started

Miscellaneous

• Fluxcursion (2017) on Energy Efficient VLSI design

• Group presentation (2013) on miniMIPS in MyHDL, see also the code on bitbucket

Personal

Jos’ Blog, mostly private notes.