Courses

• 5LIH0: Assignment videos illustrating custom digital CMOS design layout with spice simulation, design rule checking (DRC), parasitic extraction (PEX) and logic versus schematic (LVS) verification.

• 5LID0: Assignment videos illustrating CMOS synthesis, place and route.

• 5SIB0 (old, but interesting): Assignment 2: CMOS Synthesis, Place and Route.

Assignments

Master assignments and internships

In the area of error resilience and fault tolerance (Design for Error Resilience: DfER):

• Error Injection and Stability Analysis of Digital Processing Architectures
• Error-Resilient Finite State Machines

VLSI oriented assignments:

• Standard cell library for subthreshold FDSOI 28nm CMOS
• Flipflops with programmable negative setup times

Many systems have the need for multiple antenna and direction of arrival. For the linear equation need to be solved. I believe you can do this with very high performance using CORDICs:

• QRD and SVD using fixed point CORDICs

Miscellaneous

• Fluxcursion (2017) on Energy Efficient VLSI design

• Group presentation (2013) on miniMIPS in MyHDL, see also the code on bitbucket

Personal

Jos’ Blog, short CV and mostly private notes.