5SIB0 Assignment 2

5SIB0 on canvas

• Functional Validation through simulation with Cadence ncsim

• Logic Synthesis and technology mapping to 45nm CMOS with Cadence RTL compiler

• Placement and Routing to obtain a layout and parasitics in 45nm CMOS with Cadence Encounter

Partialy(mainly?) done already:

These manuals will be replaced. Things which will be tackeled are

• For accessing the server FreeNX or something similar will be advised

• Design flows will be optimized, and preferably initiated using a “git clone” instead of copying a .tar/.zip file

• Manual will be made generic to cover more use cases and courses